| /linux-6.1.9/drivers/net/phy/ |
| D | adin1100.c | 105 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg()
114 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
129 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
172 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
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| D | nxp-c45-tja11xx.c | 522 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CONFIG, in nxp_c45_perout_enable()
524 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CONFIG, in nxp_c45_perout_enable()
554 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_perout_enable()
596 phy_clear_bits_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_extts_enable()
765 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
782 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
897 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
985 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_get_status()
1103 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
1104 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
[all …]
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| D | mediatek-ge.c | 62 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); in mt7531_phy_config_init()
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| D | dp83822.c | 177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
327 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, in dp8382x_disable_wol()
413 phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_config_init()
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| D | dp83tc811.c | 151 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
350 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_config_init()
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| D | phy-c45.c | 54 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
310 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
914 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
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| D | dp83td510.c | 79 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
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| D | marvell-88x2222.c | 66 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_enable()
93 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_disable_aneg()
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| D | marvell10g.c | 328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
385 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
630 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
1329 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
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| D | adin.c | 260 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
306 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
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| D | dp83867.c | 478 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
728 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
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| D | aquantia_main.c | 704 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_resume()
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| D | mxl-gpy.c | 638 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
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| D | dp83869.c | 504 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
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| /linux-6.1.9/include/linux/ |
| D | phy.h | 1293 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, in phy_clear_bits_mmd() function
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