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Searched refs:pfit_control (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_panel.c454 u32 *pfit_control) in i965_scale_aspect() argument
465 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
468 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
471 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; in i965_scale_aspect()
475 u32 *pfit_control, u32 *pfit_pgm_ratios, in i9xx_scale_aspect() argument
501 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
516 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
522 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
534 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; in gmch_panel_fitting() local
557 i965_scale_aspect(crtc_state, &pfit_control); in gmch_panel_fitting()
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Dintel_overlay.c938 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); in update_pfit_vscale_ratio() local
948 if (pfit_control & VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
/linux-6.1.9/drivers/gpu/drm/gma500/
Dcdv_intel_lvds.c265 u32 pfit_control; in cdv_intel_lvds_mode_set() local
280 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in cdv_intel_lvds_mode_set()
284 pfit_control = 0; in cdv_intel_lvds_mode_set()
286 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_lvds_mode_set()
289 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in cdv_intel_lvds_mode_set()
291 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
Dpsb_intel_lvds.c459 u32 pfit_control; in psb_intel_lvds_mode_set() local
474 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in psb_intel_lvds_mode_set()
478 pfit_control = 0; in psb_intel_lvds_mode_set()
481 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in psb_intel_lvds_mode_set()
483 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
Doaktrail_crtc.c348 u32 pfit_control; in oaktrail_panel_fitter_pipe() local
350 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
353 if ((pfit_control & PFIT_ENABLE) == 0) in oaktrail_panel_fitter_pipe()
355 return (pfit_control >> 29) & 3; in oaktrail_panel_fitter_pipe()
Dpsb_intel_display.c79 u32 pfit_control; in psb_intel_panel_fitter_pipe() local
81 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
84 if ((pfit_control & PFIT_ENABLE) == 0) in psb_intel_panel_fitter_pipe()
Dcdv_intel_display.c560 u32 pfit_control; in cdv_intel_panel_fitter_pipe() local
562 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
565 if ((pfit_control & PFIT_ENABLE) == 0) in cdv_intel_panel_fitter_pipe()
567 return (pfit_control >> 29) & 0x3; in cdv_intel_panel_fitter_pipe()
Dcdv_intel_dp.c1088 uint32_t pfit_control; in cdv_intel_dp_mode_set() local
1093 pfit_control = PFIT_ENABLE; in cdv_intel_dp_mode_set()
1095 pfit_control = 0; in cdv_intel_dp_mode_set()
1097 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_dp_mode_set()
1099 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()