Searched refs:parent_idx (Results 1 – 5 of 5) sorted by relevance
85 u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock() local87 parent_name = of_clk_get_parent_name(np, parent_idx >> 1); in sh73a0_cpg_register_clock()88 div = (parent_idx & 1) + 1; in sh73a0_cpg_register_clock()
176 collection->parent_idx = (collection->level == 0) ? -1 : in open_collection()1078 while (collection->parent_idx != -1 && in hid_apply_multiplier_to_field()1080 collection = &hid->collection[collection->parent_idx]; in hid_apply_multiplier_to_field()1082 if (collection->parent_idx != -1 || in hid_apply_multiplier_to_field()1118 while (multiplier_collection->parent_idx != -1 && in hid_apply_multiplier()1120 multiplier_collection = &hid->collection[multiplier_collection->parent_idx]; in hid_apply_multiplier()
1083 int parent_idx; member1130 parent_clock_idx = uart_clock_base->parent_idx; in mvebu_uart_clock_prepare()1507 uart_clock_base->parent_idx = parent_clk_idx; in mvebu_uart_clock_probe()
1140 int parent_idx, in bcm2835_clock_choose_div_and_prate() argument1153 parent = clk_hw_get_parent_by_index(hw, parent_idx); in bcm2835_clock_choose_div_and_prate()1155 if (!(BIT(parent_idx) & data->set_rate_parent)) { in bcm2835_clock_choose_div_and_prate()
434 int parent_idx; /* device->collection */ member