| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dccg.c | 47 uint32_t otg_inst, in dccg32_get_pixel_rate_div() argument
57 switch (otg_inst) { in dccg32_get_pixel_rate_div()
89 uint32_t otg_inst, in dccg32_set_pixel_rate_div() argument
104 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg32_set_pixel_rate_div()
108 switch (otg_inst) { in dccg32_set_pixel_rate_div()
138 uint32_t otg_inst) in dccg32_set_dtbclk_p_src() argument
146 switch (otg_inst) { in dccg32_set_dtbclk_p_src()
206 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg32_set_dtbclk_dto()
207 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg32_set_dtbclk_dto()
209 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg32_set_dtbclk_dto()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dccg.c | 50 uint32_t otg_inst, in dccg314_get_pixel_rate_div() argument
60 switch (otg_inst) { in dccg314_get_pixel_rate_div()
92 uint32_t otg_inst, in dccg314_set_pixel_rate_div() argument
106 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
110 switch (otg_inst) { in dccg314_set_pixel_rate_div()
140 uint32_t otg_inst) in dccg314_set_dtbclk_p_src() argument
149 switch (otg_inst) { in dccg314_set_dtbclk_p_src()
209 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg314_set_dtbclk_dto()
210 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg314_set_dtbclk_dto()
212 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 109 uint32_t otg_inst) in dccg2_otg_add_pixel() argument
113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
114 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_add_pixel()
115 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_add_pixel()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
117 OTG_ADD_PIXEL[otg_inst], 1); in dccg2_otg_add_pixel()
121 uint32_t otg_inst) in dccg2_otg_drop_pixel() argument
125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
126 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_drop_pixel()
127 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_drop_pixel()
[all …]
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| D | dcn20_dccg.h | 302 uint32_t otg_inst);
304 uint32_t otg_inst);
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| D | dcn20_hubp.h | 361 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dccg.c | 97 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk() argument
102 switch (otg_inst) { in dccg31_enable_dpstreamclk()
129 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_disable_dpstreamclk() argument
138 switch (otg_inst) { in dccg31_disable_dpstreamclk()
164 int otg_inst, in dccg31_set_dpstreamclk() argument
168 dccg31_disable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
170 dccg31_enable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
551 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg31_set_dtbclk_dto()
552 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); in dccg31_set_dtbclk_dto()
554 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg31_set_dtbclk_dto()
[all …]
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| D | dcn31_dccg.h | 205 int otg_inst,
214 uint32_t otg_inst);
218 uint32_t otg_inst);
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| D | dcn31_hpo_dp_stream_encoder.c | 679 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, &s->otg_inst); in dcn31_hpo_dp_stream_enc_read_state()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dccg.h | 78 int otg_inst; member
96 uint32_t otg_inst);
98 uint32_t otg_inst);
104 int otg_inst,
153 uint32_t otg_inst,
160 int otg_inst,
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| D | abm.h | 57 bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
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| D | dwb.h | 175 int otg_inst; member
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| D | hubp.h | 166 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
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| D | stream_encoder.h | 262 uint32_t otg_inst; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 140 static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_i… in dmub_abm_set_pipe() argument
149 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; in dmub_abm_set_pipe()
165 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable() local
176 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, in dcn21_set_abm_immediate_disable()
185 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_pipe() local
195 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst); in dcn21_set_pipe()
205 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_backlight_level() local
214 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst); in dcn21_set_backlight_level()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/ |
| D | dm_cp_psp.h | 32 uint8_t otg_inst; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_crtc.c | 80 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; in dm_set_vupdate_irq()
164 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; in dm_set_vblank()
450 acrtc->otg_inst = -1; in amdgpu_dm_crtc_init()
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| D | amdgpu_dm_irq.c | 719 if (acrtc->otg_inst == -1) in dm_irq_state()
722 irq_source = dal_irq_type + acrtc->otg_inst; in dm_irq_state()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_hwss_hpo_dp.c | 113 dto_params.otg_inst = tg->inst; in setup_hpo_dp_stream_encoder()
134 dto_params.otg_inst = tg->inst; in reset_hpo_dp_stream_encoder()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_subvp_state.h | 79 uint8_t otg_inst; member
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| D | dmub_cmd.h | 563 uint32_t otg_inst: 3; member
1776 uint8_t otg_inst; member
2375 uint8_t otg_inst; member
2591 uint8_t otg_inst; member
2863 uint8_t otg_inst; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 358 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
360 copy_settings_data->otg_inst = 0; in dmub_psr_copy_settings()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_lib.c | 241 dml_print("DML PARAMS: otg_inst = %d\n", pipe_dest->otg_inst); in dml_log_pipe_params()
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| D | display_mode_structs.h | 527 unsigned char otg_inst; member
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_mode.h | 419 int otg_inst; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.c | 1285 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) in hubp1_vtg_sel() argument
1289 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); in hubp1_vtg_sel()
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