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Searched refs:opp_cnt (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_hwseq.c75 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
80 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
91 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
102 int opp_cnt = 1; in update_dsc_on_stream() local
106 opp_cnt++; in update_dsc_on_stream()
114 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream()
120 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
121 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
132 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
133 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
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Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
56 int mpcc_hactive = h_active / opp_cnt; in optc314_set_odm_combine()
65 if (opp_cnt == 4) { in optc314_set_odm_combine()
84 if (opp_cnt == 2) { in optc314_set_odm_combine()
89 } else if (opp_cnt == 4) { in optc314_set_odm_combine()
102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
103 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
Ddcn314_dio_stream_encoder.c301 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc314_stream_encoder_dp_unblank()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c210 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
215 / opp_cnt; in optc3_set_odm_combine()
226 ASSERT(opp_cnt == 2 || opp_cnt == 4); in optc3_set_odm_combine()
231 if (opp_cnt == 2) { in optc3_set_odm_combine()
236 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
247 if (opp_cnt == 2) { in optc3_set_odm_combine()
252 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
264 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
265 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
48 / opp_cnt; in optc31_set_odm_combine()
53 if (opp_cnt == 4) { in optc31_set_odm_combine()
73 if (opp_cnt == 2) { in optc31_set_odm_combine()
78 } else if (opp_cnt == 4) { in optc31_set_odm_combine()
90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
91 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
51 int mpcc_hactive = h_active / opp_cnt; in optc32_set_odm_combine()
60 if (opp_cnt == 4) { in optc32_set_odm_combine()
79 if (opp_cnt == 2) { in optc32_set_odm_combine()
84 } else if (opp_cnt == 4) { in optc32_set_odm_combine()
97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
98 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
Ddcn32_hwseq.c995 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
1000 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
1011 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
1022 int opp_cnt = 1; in update_dsc_on_stream() local
1026 opp_cnt++; in update_dsc_on_stream()
1034 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream()
1040 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
1041 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
1052 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
1053 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
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Ddcn32_dio_stream_encoder.c294 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc32_stream_encoder_dp_unblank()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
186 / opp_cnt; in optc2_set_odm_combine()
189 ASSERT(opp_cnt == 2); in optc2_set_odm_combine()
219 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
Ddcn20_hwseq.c625 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
630 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
641 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
657 int opp_cnt = 1; in dcn20_enable_stream_timing() local
685 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; in dcn20_enable_stream_timing()
686 opp_cnt++; in dcn20_enable_stream_timing()
689 if (opp_cnt > 1) in dcn20_enable_stream_timing()
692 opp_inst, opp_cnt, in dcn20_enable_stream_timing()
730 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; in dcn20_enable_stream_timing()
733 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); in dcn20_enable_stream_timing()
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Ddcn20_optc.h107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
Ddcn20_resource.c1238 int opp_cnt = 1; in get_pixel_clock_parameters() local
1245 opp_cnt++; in get_pixel_clock_parameters()
1268 if (opp_cnt == 4) in get_pixel_clock_parameters()
1270 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) in get_pixel_clock_parameters()
1663 int opp_cnt = 1; in dcn20_validate_dsc() local
1666 opp_cnt++; in dcn20_validate_dsc()
1673 + stream->timing.h_border_right) / opp_cnt; in dcn20_validate_dsc()
1680 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
Ddcn20_stream_encoder.c466 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc2_stream_encoder_dp_unblank()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Dstream_encoder.h93 int opp_cnt; member
Dtiming_generator.h304 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c5971 int opp_cnt = 1; in set_crtc_test_pattern() local
5994 opp_cnt++; in set_crtc_test_pattern()
5995 dpg_width = width / opp_cnt; in set_crtc_test_pattern()
6038 int opp_cnt = 1; in set_crtc_test_pattern() local
6042 opp_cnt++; in set_crtc_test_pattern()
6044 dpg_width = width / opp_cnt; in set_crtc_test_pattern()
7405 int opp_cnt = 1; in dp_set_dsc_on_stream() local
7408 opp_cnt++; in dp_set_dsc_on_stream()
7416 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in dp_set_dsc_on_stream()
7422 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in dp_set_dsc_on_stream()
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