Searched refs:num_uclk_states (Results 1 – 5 of 5) sorted by relevance
207 unsigned int num_uclk_states; in dcn302_fpu_update_bw_bounding_box() local258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()261 for (i = 0; i < num_uclk_states; i++) { in dcn302_fpu_update_bw_bounding_box()270 for (j = 0; j < num_uclk_states; j++) { in dcn302_fpu_update_bw_bounding_box()282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()287 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()291 j = num_uclk_states; in dcn302_fpu_update_bw_bounding_box()301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
203 unsigned int num_uclk_states; in dcn303_fpu_update_bw_bounding_box() local252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()255 for (i = 0; i < num_uclk_states; i++) { in dcn303_fpu_update_bw_bounding_box()264 for (j = 0; j < num_uclk_states; j++) { in dcn303_fpu_update_bw_bounding_box()276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()281 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()286 j = num_uclk_states; in dcn303_fpu_update_bw_bounding_box()296 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
564 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn321_update_bw_bounding_box_fpu() local602 num_uclk_states = bw_params->clk_table.num_entries; in dcn321_update_bw_bounding_box_fpu()605 for (i = 0; i < num_uclk_states; i++) { in dcn321_update_bw_bounding_box_fpu()615 for (j = 0; j < num_uclk_states; j++) { in dcn321_update_bw_bounding_box_fpu()627 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()632 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()636 j = num_uclk_states; in dcn321_update_bw_bounding_box_fpu()646 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
2110 unsigned int num_uclk_states; in dcn30_update_bw_bounding_box() local2156 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()2159 for (i = 0; i < num_uclk_states; i++) { in dcn30_update_bw_bounding_box()2171 for (j = 0; j < num_uclk_states; j++) { in dcn30_update_bw_bounding_box()2183 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2188 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2192 j = num_uclk_states; in dcn30_update_bw_bounding_box()2202 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
2407 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local2450 num_uclk_states = bw_params->clk_table.num_entries; in dcn32_update_bw_bounding_box_fpu()2453 for (i = 0; i < num_uclk_states; i++) { in dcn32_update_bw_bounding_box_fpu()2463 for (j = 0; j < num_uclk_states; j++) { in dcn32_update_bw_bounding_box_fpu()2475 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()2480 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()2484 j = num_uclk_states; in dcn32_update_bw_bounding_box_fpu()2494 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()