| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| D | dcn302_fpu.c | 126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| D | dcn303_fpu.c | 125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
283 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
293 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/arch/powerpc/kernel/ |
| D | rtas-proc.c | 508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| D | dcn321_fpu.c | 122 .num_states = 1,
556 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
627 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
629 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
630 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
633 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
634 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
641 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
642 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
643 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
344 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
369 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
371 s[dcn3_01_soc.num_states] = in dcn301_update_bw_bounding_box()
372 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_update_bw_bounding_box()
373 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
|
| /linux-6.1.9/drivers/regulator/ |
| D | irq_helpers.c | 62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
427 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 123 .num_states = 1,
269 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
369 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
370 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
410 …else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states -… in dcn32_predict_pipe_split()
1094 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1108 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1134 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1155 if (*vlevel < context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1159 } else if (*vlevel < context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
[all …]
|
| D | display_mode_vba_32.c | 113 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1641 for (i = v->soc.num_states - 1; i >= 0; i--) { in mode_support_configuration()
1692 || i == v->soc.num_states - 1 in mode_support_configuration()
1694 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
2011 for (i = 0; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2026 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2049 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2288 for (i = 0; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
2388 for (i = 0; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
2405 for (i = 0; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 169 .num_states = 5,
412 .num_states = 5,
586 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
618 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
683 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
734 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
744 closest_clk_lvl = dcn3_16_soc.num_states - 1; in dcn316_update_bw_bounding_box()
779 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
|
| D | display_mode_vba_31.c | 2128 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4064 for (i = 0; i < v->soc.num_states; i++) {
4074 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4075 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4082 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4083 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4090 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4091 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4219 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4220 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
|
| /linux-6.1.9/net/netfilter/ipvs/ |
| D | ip_vs_proto_ah_esp.c | 119 .num_states = 1,
141 .num_states = 1,
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1681 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1684 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1697 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1706 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1873 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2085 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2101 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2183 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2185 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2186 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 148 .num_states = 5,
216 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
224 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
258 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
|
| D | display_mode_vba_314.c | 2150 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4161 for (i = 0; i < v->soc.num_states; i++) {
4171 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4172 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4179 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4180 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4187 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4188 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4317 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4318 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 289 .num_states = 5,
400 .num_states = 5,
654 .num_states = 8
1690 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) in dcn20_update_bounding_box() argument
1698 if (num_states == 0) in dcn20_update_bounding_box()
1714 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1745 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1749 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1761 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
1796 for (i = bb->num_states - 1; i > 1; i--) { in dcn20_cap_soc_clocks()
[all …]
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| D | dcn20_fpu.h | 61 unsigned int num_states);
|
| D | display_mode_vba_20.c | 1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
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| D | display_mode_vba_20v2.c | 1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
|
| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 78 uint32_t num_states; member
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 229 unsigned int *clock_values_in_khz, unsigned int *num_states);
|
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1891 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1896 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2045 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2118 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2343 unsigned int num_states = 0; in init_soc_bounding_box() local
2350 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2365 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2367 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2571 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2579 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_mode_vba_30.c | 1990 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3855 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3864 …utODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3865 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3870 …MCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3871 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3876 …MCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3877 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3985 …(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->so… in dml30_ModeSupportAndSystemConfigurationFull()
4011 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_mode_vba_21.c | 1644 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3674 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3716 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4070 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4072 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml21_ModeSupportAndSystemConfigurationFull()
4094 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4101 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4178 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull()
4210 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4227 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 708 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
716 num_states); in pp_nv_get_uclk_dpm_states()
|
| /linux-6.1.9/include/linux/regulator/ |
| D | driver.h | 496 int num_states; member
|