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Searched refs:nCur40MhzPrimeSC (Results 1 – 14 of 14) sorted by relevance

/linux-6.1.9/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c611 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) in phy_GetSecondaryChnl_8723B()
613 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) in phy_GetSecondaryChnl_8723B()
653 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); in phy_PostSetBwMode8723B()
655 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); in phy_PostSetBwMode8723B()
657 …PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_L… in phy_PostSetBwMode8723B()
714 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC; in PHY_HandleSwChnlAndSetBW8723B()
745 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz; in PHY_HandleSwChnlAndSetBW8723B()
761 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; in PHY_HandleSwChnlAndSetBW8723B()
Drtl8723b_dm.c94 ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); in Update_ODM_ComInfo_8723b()
Drtl8723b_hal_init.c2487 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) { in SCMapping_8723B()
2489 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) { in SCMapping_8723B()
/linux-6.1.9/drivers/staging/r8188eu/hal/
Drtl8188e_phycfg.c613 regRRSR_RSC = (regRRSR_RSC & 0x90) | (pHalData->nCur40MhzPrimeSC << 5); in _PHY_SetBWMode92C()
634 rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); in _PHY_SetBWMode92C()
635 rtl8188e_PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); in _PHY_SetBWMode92C()
637 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); in _PHY_SetBWMode92C()
669 pHalData->nCur40MhzPrimeSC = Offset; in PHY_SetBWMode8188E()
Drtl8188e_dm.c46 dm_odm->pSecChOffset = &hal_data->nCur40MhzPrimeSC; in Update_ODM_ComInfo_88E()
/linux-6.1.9/drivers/staging/r8188eu/include/
Drtl8188e_hal.h104 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ member
/linux-6.1.9/drivers/staging/rtl8192u/
Dr819xU_phy.c1534 priv->nCur40MhzPrimeSC >> 1); in rtl8192_SetBWModeWorkItem()
1537 priv->nCur40MhzPrimeSC); in rtl8192_SetBWModeWorkItem()
1619 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; in rtl8192_SetBWMode()
1621 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; in rtl8192_SetBWMode()
1623 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; in rtl8192_SetBWMode()
Dr8192U.h960 u8 nCur40MhzPrimeSC; member
Dr8192U_core.c1287 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC; in rtl8192_tx()
/linux-6.1.9/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c1160 (priv->nCur40MhzPrimeSC>>1)); in _rtl92e_set_bw_mode_work_item()
1162 priv->nCur40MhzPrimeSC); in _rtl92e_set_bw_mode_work_item()
1212 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; in rtl92e_set_bw_mode()
1214 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; in rtl92e_set_bw_mode()
1216 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; in rtl92e_set_bw_mode()
Drtl_core.h465 u8 nCur40MhzPrimeSC; member
Dr8192E_dev.c1085 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; in rtl92e_fill_tx_desc()
/linux-6.1.9/drivers/staging/rtl8723bs/include/
Dhal_data.h180 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ member
/linux-6.1.9/drivers/staging/r8188eu/core/
Drtw_wlan_util.c1385 val8 = haldata->nCur40MhzPrimeSC << 5; in set_ack_preamble()