| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_mpc.c | 48 int mpcc_id; in mpc32_mpc_init() local
54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { in mpc32_mpc_init()
55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) in mpc32_mpc_init()
62 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3); in mpc32_mpc_init()
69 uint32_t mpcc_id, in mpc32_power_on_blnd_lut() argument
76 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); in mpc32_power_on_blnd_lut()
77 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5); in mpc32_power_on_blnd_lut()
[all …]
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| D | dcn32_hwseq.c | 520 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut() local
542 mpcc_id); in dcn32_set_mpc_shaper_3dlut()
546 mpcc_id); in dcn32_set_mpc_shaper_3dlut()
556 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts() local
572 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
588 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
592 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); in dcn32_set_mcm_luts()
594 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); in dcn32_set_mcm_luts()
645 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func() local
669 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn32_set_output_transfer_func()
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| D | dcn32_hubp.c | 207 hubp2->base.mpcc_id = 0xf; in hubp32_construct()
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| D | dcn32_resource.c | 1607 int mpcc_id, in dcn32_acquire_post_bldn_3dlut() argument
1618 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1619 *lut = pool->mpc_lut[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1620 *shaper = pool->mpc_shaper[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1621 state = &pool->mpc_lut[mpcc_id]->state; in dcn32_acquire_post_bldn_3dlut()
1622 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 42 int mpcc_id) in mpc1_set_bg_color() argument
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
79 int mpcc_id) in mpc1_update_blending() argument
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending()
84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], in mpc1_update_blending()
97 int mpcc_id) in mpc1_update_stereo_mix() argument
101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], in mpc1_update_stereo_mix()
[all …]
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| D | dcn10_mpc.h | 148 int mpcc_id);
160 unsigned int mpcc_id);
174 int mpcc_id);
178 int mpcc_id);
182 int mpcc_id);
190 int mpcc_id);
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| D | dcn10_hw_sequencer.h | 206 int mpcc_id);
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| D | dcn10_hw_sequencer.c | 1400 hubp->mpcc_id = dpp->inst; in dcn10_init_pipes()
2583 …visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) in dcn10_update_visual_confirm_color() argument
2599 mpc->funcs->set_bg_color(mpc, color, mpcc_id); in dcn10_update_visual_confirm_color()
2608 int mpcc_id; in dcn10_update_mpcc() local
2647 mpcc_id = hubp->inst; in dcn10_update_mpcc()
2651 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn10_update_mpcc()
2652 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); in dcn10_update_mpcc()
2657 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); in dcn10_update_mpcc()
2664 dc->res_pool->mpc, mpcc_id); in dcn10_update_mpcc()
2673 mpcc_id); in dcn10_update_mpcc()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 51 int mpcc_id) in mpc2_update_blending() argument
55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending()
57 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], in mpc2_update_blending()
66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
273 struct mpc *mpc, int mpcc_id, in mpc20_power_on_ogam_lut() argument
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
284 struct mpc *mpc, int mpcc_id, in mpc20_configure_ogam_lut() argument
289 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], in mpc20_configure_ogam_lut()
[all …]
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| D | dcn20_mpc.h | 280 int mpcc_id);
306 int mpcc_id,
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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| D | dcn20_hwseq.c | 805 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_program_output_csc() local
808 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_program_output_csc()
828 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_set_output_transfer_func() local
839 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_set_output_transfer_func()
859 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn20_set_output_transfer_func()
2474 …visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) in dcn20_update_visual_confirm_color() argument
2492 mpc->funcs->set_bg_color(mpc, color, mpcc_id); in dcn20_update_visual_confirm_color()
2501 int mpcc_id; in dcn20_update_mpcc() local
2545 mpcc_id = hubp->inst; in dcn20_update_mpcc()
2550 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn20_update_mpcc()
[all …]
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| D | dcn20_hwseq.h | 156 int mpcc_id);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_mpc.c | 65 int mpcc_id) in mpc3_set_dwb_mux() argument
70 MPC_DWB0_MUX, mpcc_id); in mpc3_set_dwb_mux()
102 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) in mpc3_get_ogam_current() argument
112 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode, in mpc3_get_ogam_current()
141 struct mpc *mpc, int mpcc_id, in mpc3_power_on_ogam_lut() argument
152 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], in mpc3_power_on_ogam_lut()
157 REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); in mpc3_power_on_ogam_lut()
161 struct mpc *mpc, int mpcc_id, in mpc3_configure_ogam_lut() argument
166 REG_UPDATE_2(MPCC_OGAM_LUT_CONTROL[mpcc_id], in mpc3_configure_ogam_lut()
170 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc3_configure_ogam_lut()
[all …]
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| D | dcn30_resource.h | 85 int mpcc_id,
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| D | dcn30_hwseq.c | 98 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut() local
126 if (mpcc_id_projected != mpcc_id) in dcn30_set_mpc_shaper_3dlut()
129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
140 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func() local
217 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
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| D | dcn30_mpc.h | 1022 int mpcc_id, int rmu_idx);
1048 int mpcc_id,
1057 int mpcc_id,
1068 int mpcc_id);
1086 struct mpc *mpc, int mpcc_id,
1093 int mpcc_id);
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| D | dcn30_hubp.c | 527 hubp2->base.mpcc_id = 0xf; in hubp3_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 157 int mpcc_id; /* MPCC physical instance */ member
232 int mpcc_id);
264 unsigned int mpcc_id);
281 int mpcc_id);
326 int mpcc_id);
354 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
381 int mpcc_id,
385 int mpcc_id,
390 int mpcc_id);
409 int mpcc_id,
[all …]
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| D | hubp.h | 65 int mpcc_id; member
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hwseq.c | 326 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
440 int mpcc_id, dpp_id; in dcn201_update_mpcc() local
495 mpcc_id = dpp_id; in dcn201_update_mpcc()
499 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); in dcn201_update_mpcc()
500 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); in dcn201_update_mpcc()
521 dc->res_pool->mpc, mpcc_id); in dcn201_update_mpcc()
524 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); in dcn201_update_mpcc()
531 mpcc_id); in dcn201_update_mpcc()
535 hubp->mpcc_id = mpcc_id; in dcn201_update_mpcc()
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| D | dcn201_mpc.c | 64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| D | dcn201_hubp.c | 146 hubp201->base.mpcc_id = 0xf; in dcn201_hubp_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hubp.c | 110 hubp2->base.mpcc_id = 0xf; in hubp31_construct()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 261 int mpcc_id);
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| D | core_types.h | 215 int mpcc_id,
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