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Searched refs:mmVGA_HDP_CONTROL (Results 1 – 19 of 19) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c246 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
248 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v6_0_mc_program()
Dgmc_v7_0.c280 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
282 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v7_0_mc_program()
Dgmc_v8_0.c462 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
464 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
Ddce_v8_0.c383 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v8_0_set_vga_render_state()
388 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
Ddce_v10_0.c450 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v10_0_set_vga_render_state()
455 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
Ddce_v11_0.c466 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_set_vga_render_state()
471 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h4383 #define mmVGA_HDP_CONTROL 0x00CA macro
Ddce_8_0_d.h5142 #define mmVGA_HDP_CONTROL 0xca macro
Ddce_10_0_d.h6025 #define mmVGA_HDP_CONTROL 0xca macro
Ddce_11_0_d.h6102 #define mmVGA_HDP_CONTROL 0xca macro
Ddce_11_2_d.h7776 #define mmVGA_HDP_CONTROL 0xca macro
Ddce_12_0_offset.h570 #define mmVGA_HDP_CONTROL … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h33 #define mmVGA_HDP_CONTROL … macro
Ddcn_3_0_1_offset.h164 #define mmVGA_HDP_CONTROL … macro
Ddcn_1_0_offset.h404 #define mmVGA_HDP_CONTROL … macro
Ddcn_2_1_0_offset.h108 #define mmVGA_HDP_CONTROL … macro
Ddcn_3_0_2_offset.h48 #define mmVGA_HDP_CONTROL … macro
Ddcn_2_0_0_offset.h48 #define mmVGA_HDP_CONTROL … macro
Ddcn_3_0_0_offset.h29 #define mmVGA_HDP_CONTROL … macro