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Searched refs:mmVCE_MMSCH_VF_MAILBOX_RESP (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_4_0_offset.h198 #define mmVCE_MMSCH_VF_MAILBOX_RESP … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvce_v4_0.c177 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); in vce_v4_0_mmsch_start()
187 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
191 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
Duvd_v7_0.c751 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); in uvd_v7_0_mmsch_start()
764 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); in uvd_v7_0_mmsch_start()
768 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); in uvd_v7_0_mmsch_start()