| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 92 #define mmUVD_VCPU_CACHE_SIZE1 0x3D39 macro
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| D | uvd_4_2_d.h | 63 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
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| D | uvd_3_1_d.h | 65 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
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| D | uvd_5_0_d.h | 69 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
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| D | uvd_6_0_d.h | 85 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
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| D | uvd_7_0_offset.h | 184 #define mmUVD_VCPU_CACHE_SIZE1 … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 370 #define mmUVD_VCPU_CACHE_SIZE1 … macro
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| D | vcn_2_5_offset.h | 691 #define mmUVD_VCPU_CACHE_SIZE1 … macro
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| D | vcn_2_0_0_offset.h | 620 #define mmUVD_VCPU_CACHE_SIZE1 … macro
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| D | vcn_3_0_0_offset.h | 1067 #define mmUVD_VCPU_CACHE_SIZE1 … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_mc_resume()
448 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1928 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), in vcn_v2_0_start_sriov()
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| D | uvd_v3_1.c | 254 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v3_1_mc_resume()
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| D | uvd_v4_2.c | 583 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 295 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v5_0_mc_resume()
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| D | vcn_v2_5.c | 429 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
514 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1240 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
559 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1372 mmUVD_VCPU_CACHE_SIZE1), in vcn_v3_0_start_sriov()
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| D | uvd_v7_0.c | 705 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); in uvd_v7_0_mc_resume()
848 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE… in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v1_0_mc_resume_spg_mode()
404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 619 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v6_0_mc_resume()
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