| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 89 #define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 macro
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| D | uvd_4_2_d.h | 62 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| D | uvd_3_1_d.h | 64 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| D | uvd_5_0_d.h | 68 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| D | uvd_6_0_d.h | 84 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| D | uvd_7_0_offset.h | 182 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 368 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| D | vcn_2_5_offset.h | 689 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| D | vcn_2_0_0_offset.h | 618 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| D | vcn_3_0_0_offset.h | 1065 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 361 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_0_mc_resume()
438 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
445 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1925 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), in vcn_v2_0_start_sriov()
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| D | vcn_v2_5.c | 428 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
504 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
511 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1237 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v3_0_mc_resume()
549 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1369 mmUVD_VCPU_CACHE_OFFSET1), in vcn_v3_0_start_sriov()
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| D | uvd_v3_1.c | 253 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); in uvd_v3_1_mc_resume()
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| D | uvd_v4_2.c | 582 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 294 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v5_0_mc_resume()
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| D | uvd_v7_0.c | 704 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); in uvd_v7_0_mc_resume()
847 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v1_0_mc_resume_spg_mode()
402 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 618 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v6_0_mc_resume()
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