Searched refs:mmUVD_RB_SIZE (Results 1 – 12 of 12) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_d.h | 46 #define mmUVD_RB_SIZE 0x3c28 macro
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| D | uvd_7_0_offset.h | 98 #define mmUVD_RB_SIZE … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 220 #define mmUVD_RB_SIZE … macro
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| D | vcn_2_5_offset.h | 555 #define mmUVD_RB_SIZE … macro
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| D | vcn_2_0_0_offset.h | 932 #define mmUVD_RB_SIZE … macro
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| D | vcn_3_0_0_offset.h | 885 #define mmUVD_RB_SIZE … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 1087 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_start()
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1958 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), in vcn_v2_0_start_sriov()
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| D | vcn_v2_5.c | 1094 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1269 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), in vcn_v2_5_sriov_start()
1443 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
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| D | vcn_v3_0.c | 1264 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_start()
1401 mmUVD_RB_SIZE), in vcn_v3_0_start_sriov()
1638 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
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| D | uvd_v7_0.c | 921 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); in uvd_v7_0_sriov_start()
1116 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); in uvd_v7_0_start()
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| D | vcn_v1_0.c | 946 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
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| D | uvd_v6_0.c | 867 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); in uvd_v6_0_start()
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