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Searched refs:mmUVD_RB_RPTR2 (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h42 #define mmUVD_RB_RPTR2 0x3c24 macro
Duvd_7_0_offset.h90 #define mmUVD_RB_RPTR2 … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h212 #define mmUVD_RB_RPTR2 … macro
Dvcn_2_5_offset.h567 #define mmUVD_RB_RPTR2 … macro
Dvcn_2_0_0_offset.h924 #define mmUVD_RB_RPTR2 … macro
Dvcn_3_0_0_offset.h897 #define mmUVD_RB_RPTR2 … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c949 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1254 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1592 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v1_0_enc_ring_get_rptr()
Dvcn_v2_0.c1092 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1555 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v2_0_enc_ring_get_rptr()
Dvcn_v2_5.c1099 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1319 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1454 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1603 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
Dvcn_v3_0.c1269 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1506 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1649 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1939 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v3_0_enc_ring_get_rptr()
Duvd_v6_0.c98 return RREG32(mmUVD_RB_RPTR2); in uvd_v6_0_enc_ring_get_rptr()
870 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Duvd_v7_0.c92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
1119 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()