Searched refs:mmUVD_RB_BASE_LO2 (Results 1 – 12 of 12) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_d.h | 39 #define mmUVD_RB_BASE_LO2 0x3c21 macro
|
| D | uvd_7_0_offset.h | 84 #define mmUVD_RB_BASE_LO2 … macro
|
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 206 #define mmUVD_RB_BASE_LO2 … macro
|
| D | vcn_2_5_offset.h | 561 #define mmUVD_RB_BASE_LO2 … macro
|
| D | vcn_2_0_0_offset.h | 918 #define mmUVD_RB_BASE_LO2 … macro
|
| D | vcn_3_0_0_offset.h | 891 #define mmUVD_RB_BASE_LO2 … macro
|
| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v1_0.c | 951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
|
| D | vcn_v2_0.c | 1094 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
|
| D | vcn_v2_5.c | 1101 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1451 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
|
| D | vcn_v3_0.c | 1271 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_start()
1646 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
|
| D | uvd_v6_0.c | 872 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v6_0_start()
|
| D | uvd_v7_0.c | 1121 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v7_0_start()
|