| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 52 #define mmUVD_MASTINT_EN 0x3D40 macro
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| D | uvd_4_2_d.h | 47 #define mmUVD_MASTINT_EN 0x3d40 macro
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| D | uvd_3_1_d.h | 47 #define mmUVD_MASTINT_EN 0x3d40 macro
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| D | uvd_5_0_d.h | 53 #define mmUVD_MASTINT_EN 0x3d40 macro
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| D | uvd_6_0_d.h | 69 #define mmUVD_MASTINT_EN 0x3d40 macro
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| D | uvd_7_0_offset.h | 152 #define mmUVD_MASTINT_EN … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 330 #define mmUVD_MASTINT_EN … macro
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| D | vcn_2_5_offset.h | 533 #define mmUVD_MASTINT_EN … macro
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| D | vcn_2_0_0_offset.h | 538 #define mmUVD_MASTINT_EN … macro
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| D | vcn_3_0_0_offset.h | 863 #define mmUVD_MASTINT_EN … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 344 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
409 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v3_1_start()
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| D | uvd_v4_2.c | 302 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
367 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
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| D | uvd_v5_0.c | 333 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
410 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
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| D | uvd_v7_0.c | 866 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
903 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
979 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start()
1070 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
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| D | vcn_v1_0.c | 805 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode()
895 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start_spg_mode()
987 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1041 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
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| D | vcn_v2_0.c | 821 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
877 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start_dpg_mode()
957 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start()
1047 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start()
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| D | vcn_v2_5.c | 803 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
863 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
957 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1053 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
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| D | vcn_v3_0.c | 969 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1029 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v3_0_start()
1218 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v3_0_start()
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| D | uvd_v6_0.c | 824 WREG32_P(mmUVD_MASTINT_EN, in uvd_v6_0_start()
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