Searched refs:mmUVD_JRBC_RB_RPTR (Results 1 – 10 of 10) sorted by relevance
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
D | jpeg_v1_0.c | 117 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring() 140 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_get_rptr() 532 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v1_0_start()
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D | jpeg_v3_0.c | 366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v3_0_start() 415 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v3_0_dec_ring_get_rptr()
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D | jpeg_v2_0.c | 345 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_0_start() 395 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v2_0_dec_ring_get_rptr()
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D | jpeg_v2_5.c | 350 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_5_start() 402 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
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D | vcn_v1_0.c | 1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode() 1313 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
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/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_7_0_offset.h | 104 #define mmUVD_JRBC_RB_RPTR … macro
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/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
D | vcn_1_0_offset.h | 228 #define mmUVD_JRBC_RB_RPTR … macro
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D | vcn_2_5_offset.h | 153 #define mmUVD_JRBC_RB_RPTR … macro
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D | vcn_2_0_0_offset.h | 138 #define mmUVD_JRBC_RB_RPTR … macro
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D | vcn_3_0_0_offset.h | 351 #define mmUVD_JRBC_RB_RPTR … macro
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