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Searched refs:mmUVD_GPCOM_VCPU_CMD (Results 1 – 20 of 20) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h42 #define mmUVD_GPCOM_VCPU_CMD 0x3BC3 macro
Duvd_4_2_d.h30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
Duvd_3_1_d.h30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
Duvd_5_0_d.h30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
Duvd_6_0_d.h30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
Duvd_7_0_offset.h54 #define mmUVD_GPCOM_VCPU_CMD … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c930 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
937 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
1067 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_wreg()
1082 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
1099 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
Dvcn_v1_0.c135 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v1_0_sw_init()
1433 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_start()
1449 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_end()
1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence()
1490 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence()
1543 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_reg_wait()
1574 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_wreg()
Duvd_v3_1.c121 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence()
128 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence()
Duvd_v4_2.c483 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence()
490 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence()
Duvd_v5_0.c499 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence()
506 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence()
Duvd_v7_0.c1192 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1202 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1374 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_wreg()
1393 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_reg_wait()
Damdgpu_uvd.c1012 case mmUVD_GPCOM_VCPU_CMD: in amdgpu_uvd_cs_reg()
Dvcn_v2_0.c152 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init()
Dvcn_v2_5.c179 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
Dvcn_v3_0.c172 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); in vcn_v3_0_sw_init()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h138 #define mmUVD_GPCOM_VCPU_CMD … macro
Dvcn_2_5_offset.h511 #define mmUVD_GPCOM_VCPU_CMD … macro
Dvcn_2_0_0_offset.h810 #define mmUVD_GPCOM_VCPU_CMD … macro
Dvcn_3_0_0_offset.h827 #define mmUVD_GPCOM_VCPU_CMD … macro