Home
last modified time | relevance | path

Searched refs:mmUVD_DPG_VCPU_CACHE_OFFSET0 (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ !
Duvd_7_0_offset.h46 #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ !
Dvcn_1_0_offset.h76 #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … macro
Dvcn_2_5_offset.h451 #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … macro
Dvcn_2_0_0_offset.h436 #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … macro
Dvcn_3_0_0_offset.h727 #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … macro