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Searched refs:mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h2564 #define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX … macro
Dgc_10_3_0_offset.h2653 #define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX … macro