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Searched refs:mmSDMA0_UTCL1_WR_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h139 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
Dsdma0_4_0_offset.h141 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 macro
Dsdma0_4_2_2_offset.h141 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
Dsdma0_4_2_offset.h141 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h116 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
Dgc_10_3_0_offset.h113 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro