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Searched refs:mmRLC_GPM_TIMER_INT_0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5984 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … macro
Dgc_9_1_offset.h6206 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … macro
Dgc_9_2_1_offset.h6170 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … macro
Dgc_10_1_0_offset.h9294 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … macro
Dgc_10_3_0_offset.h9102 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX … macro