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Searched refs:mmMP1_SMN_C2PMSG_82 (Results 1 – 14 of 14) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c154 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()
Dsmu10_smumgr.c76 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu10_read_arg_from_smc()
105 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu10_send_msg_to_smc_with_parameter()
Dvega20_smumgr.c140 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in vega20_send_msg_to_smc_with_parameter()
155 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in vega20_get_argument()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_10_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
Dmp_12_0_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
Dmp_11_0_8_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
Dmp_11_0_offset.h284 #define mmMP1_SMN_C2PMSG_82 macro
Dmp_9_0_offset.h294 #define mmMP1_SMN_C2PMSG_82 0x0292 macro
Dmp_11_5_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_4_ppt.c49 #define mmMP1_SMN_C2PMSG_82 0x0292 macro
1033 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_v13_0_4_set_smu_mailbox_registers()
Dsmu_v13_0_0_ppt.c76 #define mmMP1_SMN_C2PMSG_82 macro
1927 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_v13_0_0_set_smu_mailbox_registers()
Dsmu_v13_0.c67 #define mmMP1_SMN_C2PMSG_82 macro
2446 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_v13_0_set_smu_mailbox_registers()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c47 #define mmMP1_SMN_C2PMSG_82 macro
1473 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); in renoir_set_ppt_funcs()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsmu_v11_0.c2211 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_v11_0_set_smu_mailbox_registers()