Searched refs:mmIH_RB_CNTL_RING1 (Results 1 – 7 of 7) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | navi10_ih.c | 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_init_register_offset()
114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
|
| D | vega10_ih.c | 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_init_register_offset()
|
| D | vega20_ih.c | 71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega20_ih_init_register_offset()
|
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | osssys_4_0_1_offset.h | 136 #define mmIH_RB_CNTL_RING1 … macro
|
| D | osssys_4_0_offset.h | 136 #define mmIH_RB_CNTL_RING1 … macro
|
| D | osssys_4_2_0_offset.h | 138 #define mmIH_RB_CNTL_RING1 … macro
|
| D | osssys_5_0_0_offset.h | 136 #define mmIH_RB_CNTL_RING1 … macro
|