1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_MME_ACC_REGS_H_
14 #define ASIC_REG_DCORE0_MME_ACC_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_MME_ACC
19  *   (Prototype: ACC)
20  *****************************************
21  */
22 
23 #define mmDCORE0_MME_ACC_WBC0_AXI 0x40F8000
24 
25 #define mmDCORE0_MME_ACC_WBC1_AXI 0x40F8004
26 
27 #define mmDCORE0_MME_ACC_WBC0_RL 0x40F8008
28 
29 #define mmDCORE0_MME_ACC_WBC1_RL 0x40F800C
30 
31 #define mmDCORE0_MME_ACC_WBC_STALL 0x40F8010
32 
33 #define mmDCORE0_MME_ACC_AWCACHE 0x40F8014
34 
35 #define mmDCORE0_MME_ACC_AWPROT 0x40F8018
36 
37 #define mmDCORE0_MME_ACC_AP_LFSR_POLY 0x40F801C
38 
39 #define mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA 0x40F8020
40 
41 #define mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL 0x40F8024
42 
43 #define mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA 0x40F8028
44 
45 #define mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY 0x40F802C
46 
47 #define mmDCORE0_MME_ACC_WBC_SRC_BP 0x40F8030
48 
49 #define mmDCORE0_MME_ACC_CLK_GATE_EN 0x40F8034
50 
51 #define mmDCORE0_MME_ACC_WBC_INFLIGHTS 0x40F8038
52 
53 #define mmDCORE0_MME_ACC_HBW_CLK_ENABLER_DIS 0x40F803C
54 
55 #define mmDCORE0_MME_ACC_E2E_CRDT_TOP0 0x40F8040
56 
57 #define mmDCORE0_MME_ACC_E2E_CRDT_TOP1 0x40F8044
58 
59 #define mmDCORE0_MME_ACC_INTR_CAUSE 0x40F8048
60 
61 #define mmDCORE0_MME_ACC_INTR_MASK 0x40F804C
62 
63 #define mmDCORE0_MME_ACC_INTR_CLEAR 0x40F8050
64 
65 #define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 0x40F8054
66 
67 #define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 0x40F8058
68 
69 #define mmDCORE0_MME_ACC_BIST 0x40F805C
70 
71 #define mmDCORE0_MME_ACC_WR_AXI_AGG_2P_BVALID 0x40F8060
72 
73 #endif /* ASIC_REG_DCORE0_MME_ACC_REGS_H_ */
74