1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _mmhub_2_0_0_OFFSET_HEADER 22 #define _mmhub_2_0_0_OFFSET_HEADER 23 24 25 26 // addressBlock: mmhub_dagbdec 27 // base address: 0x68000 28 #define mmDAGB0_RDCLI0 0x0000 29 #define mmDAGB0_RDCLI0_BASE_IDX 0 30 #define mmDAGB0_RDCLI1 0x0001 31 #define mmDAGB0_RDCLI1_BASE_IDX 0 32 #define mmDAGB0_RDCLI2 0x0002 33 #define mmDAGB0_RDCLI2_BASE_IDX 0 34 #define mmDAGB0_RDCLI3 0x0003 35 #define mmDAGB0_RDCLI3_BASE_IDX 0 36 #define mmDAGB0_RDCLI4 0x0004 37 #define mmDAGB0_RDCLI4_BASE_IDX 0 38 #define mmDAGB0_RDCLI5 0x0005 39 #define mmDAGB0_RDCLI5_BASE_IDX 0 40 #define mmDAGB0_RDCLI6 0x0006 41 #define mmDAGB0_RDCLI6_BASE_IDX 0 42 #define mmDAGB0_RDCLI7 0x0007 43 #define mmDAGB0_RDCLI7_BASE_IDX 0 44 #define mmDAGB0_RDCLI8 0x0008 45 #define mmDAGB0_RDCLI8_BASE_IDX 0 46 #define mmDAGB0_RDCLI9 0x0009 47 #define mmDAGB0_RDCLI9_BASE_IDX 0 48 #define mmDAGB0_RDCLI10 0x000a 49 #define mmDAGB0_RDCLI10_BASE_IDX 0 50 #define mmDAGB0_RDCLI11 0x000b 51 #define mmDAGB0_RDCLI11_BASE_IDX 0 52 #define mmDAGB0_RDCLI12 0x000c 53 #define mmDAGB0_RDCLI12_BASE_IDX 0 54 #define mmDAGB0_RDCLI13 0x000d 55 #define mmDAGB0_RDCLI13_BASE_IDX 0 56 #define mmDAGB0_RDCLI14 0x000e 57 #define mmDAGB0_RDCLI14_BASE_IDX 0 58 #define mmDAGB0_RDCLI15 0x000f 59 #define mmDAGB0_RDCLI15_BASE_IDX 0 60 #define mmDAGB0_RDCLI16 0x0010 61 #define mmDAGB0_RDCLI16_BASE_IDX 0 62 #define mmDAGB0_RDCLI17 0x0011 63 #define mmDAGB0_RDCLI17_BASE_IDX 0 64 #define mmDAGB0_RDCLI18 0x0012 65 #define mmDAGB0_RDCLI18_BASE_IDX 0 66 #define mmDAGB0_RD_CNTL 0x0013 67 #define mmDAGB0_RD_CNTL_BASE_IDX 0 68 #define mmDAGB0_RD_GMI_CNTL 0x0014 69 #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 70 #define mmDAGB0_RD_ADDR_DAGB 0x0015 71 #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 72 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0016 73 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 74 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0017 75 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 76 #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0018 77 #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 78 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0019 79 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 80 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x001a 81 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 82 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001b 83 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 84 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001c 85 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 86 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001d 87 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 88 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001e 89 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 90 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x001f 91 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 92 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0020 93 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 94 #define mmDAGB0_RD_VC0_CNTL 0x0021 95 #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 96 #define mmDAGB0_RD_VC1_CNTL 0x0022 97 #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 98 #define mmDAGB0_RD_VC2_CNTL 0x0023 99 #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 100 #define mmDAGB0_RD_VC3_CNTL 0x0024 101 #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 102 #define mmDAGB0_RD_VC4_CNTL 0x0025 103 #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 104 #define mmDAGB0_RD_VC5_CNTL 0x0026 105 #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 106 #define mmDAGB0_RD_VC6_CNTL 0x0027 107 #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 108 #define mmDAGB0_RD_VC7_CNTL 0x0028 109 #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 110 #define mmDAGB0_RD_CNTL_MISC 0x0029 111 #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 112 #define mmDAGB0_RD_TLB_CREDIT 0x002a 113 #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 114 #define mmDAGB0_RDCLI_ASK_PENDING 0x002b 115 #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 116 #define mmDAGB0_RDCLI_GO_PENDING 0x002c 117 #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 118 #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x002d 119 #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 120 #define mmDAGB0_RDCLI_TLB_PENDING 0x002e 121 #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 122 #define mmDAGB0_RDCLI_OARB_PENDING 0x002f 123 #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 124 #define mmDAGB0_RDCLI_OSD_PENDING 0x0030 125 #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 126 #define mmDAGB0_WRCLI0 0x0031 127 #define mmDAGB0_WRCLI0_BASE_IDX 0 128 #define mmDAGB0_WRCLI1 0x0032 129 #define mmDAGB0_WRCLI1_BASE_IDX 0 130 #define mmDAGB0_WRCLI2 0x0033 131 #define mmDAGB0_WRCLI2_BASE_IDX 0 132 #define mmDAGB0_WRCLI3 0x0034 133 #define mmDAGB0_WRCLI3_BASE_IDX 0 134 #define mmDAGB0_WRCLI4 0x0035 135 #define mmDAGB0_WRCLI4_BASE_IDX 0 136 #define mmDAGB0_WRCLI5 0x0036 137 #define mmDAGB0_WRCLI5_BASE_IDX 0 138 #define mmDAGB0_WRCLI6 0x0037 139 #define mmDAGB0_WRCLI6_BASE_IDX 0 140 #define mmDAGB0_WRCLI7 0x0038 141 #define mmDAGB0_WRCLI7_BASE_IDX 0 142 #define mmDAGB0_WRCLI8 0x0039 143 #define mmDAGB0_WRCLI8_BASE_IDX 0 144 #define mmDAGB0_WRCLI9 0x003a 145 #define mmDAGB0_WRCLI9_BASE_IDX 0 146 #define mmDAGB0_WRCLI10 0x003b 147 #define mmDAGB0_WRCLI10_BASE_IDX 0 148 #define mmDAGB0_WRCLI11 0x003c 149 #define mmDAGB0_WRCLI11_BASE_IDX 0 150 #define mmDAGB0_WRCLI12 0x003d 151 #define mmDAGB0_WRCLI12_BASE_IDX 0 152 #define mmDAGB0_WRCLI13 0x003e 153 #define mmDAGB0_WRCLI13_BASE_IDX 0 154 #define mmDAGB0_WRCLI14 0x003f 155 #define mmDAGB0_WRCLI14_BASE_IDX 0 156 #define mmDAGB0_WRCLI15 0x0040 157 #define mmDAGB0_WRCLI15_BASE_IDX 0 158 #define mmDAGB0_WRCLI16 0x0041 159 #define mmDAGB0_WRCLI16_BASE_IDX 0 160 #define mmDAGB0_WRCLI17 0x0042 161 #define mmDAGB0_WRCLI17_BASE_IDX 0 162 #define mmDAGB0_WRCLI18 0x0043 163 #define mmDAGB0_WRCLI18_BASE_IDX 0 164 #define mmDAGB0_WR_CNTL 0x0044 165 #define mmDAGB0_WR_CNTL_BASE_IDX 0 166 #define mmDAGB0_WR_GMI_CNTL 0x0045 167 #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 168 #define mmDAGB0_WR_ADDR_DAGB 0x0046 169 #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 170 #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0047 171 #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 172 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0048 173 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 174 #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0049 175 #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 176 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x004a 177 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 178 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x004b 179 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 180 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x004c 181 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 182 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x004d 183 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 184 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x004e 185 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 186 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x004f 187 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 188 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0050 189 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 190 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0051 191 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 192 #define mmDAGB0_WR_DATA_DAGB 0x0052 193 #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 194 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0053 195 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 196 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0054 197 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 198 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0055 199 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 200 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0056 201 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 202 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0057 203 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 204 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0058 205 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 206 #define mmDAGB0_WR_VC0_CNTL 0x0059 207 #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 208 #define mmDAGB0_WR_VC1_CNTL 0x005a 209 #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 210 #define mmDAGB0_WR_VC2_CNTL 0x005b 211 #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 212 #define mmDAGB0_WR_VC3_CNTL 0x005c 213 #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 214 #define mmDAGB0_WR_VC4_CNTL 0x005d 215 #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 216 #define mmDAGB0_WR_VC5_CNTL 0x005e 217 #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 218 #define mmDAGB0_WR_VC6_CNTL 0x005f 219 #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 220 #define mmDAGB0_WR_VC7_CNTL 0x0060 221 #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 222 #define mmDAGB0_WR_CNTL_MISC 0x0061 223 #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 224 #define mmDAGB0_WR_TLB_CREDIT 0x0062 225 #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 226 #define mmDAGB0_WR_DATA_CREDIT 0x0063 227 #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 228 #define mmDAGB0_WR_MISC_CREDIT 0x0064 229 #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 230 #define mmDAGB0_WRCLI_ASK_PENDING 0x0065 231 #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 232 #define mmDAGB0_WRCLI_GO_PENDING 0x0066 233 #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 234 #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x0067 235 #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 236 #define mmDAGB0_WRCLI_TLB_PENDING 0x0068 237 #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 238 #define mmDAGB0_WRCLI_OARB_PENDING 0x0069 239 #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 240 #define mmDAGB0_WRCLI_OSD_PENDING 0x006a 241 #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 242 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x006b 243 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 244 #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x006c 245 #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 246 #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x006d 247 #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 248 #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x006e 249 #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 250 #define mmDAGB0_DAGB_DLY 0x006f 251 #define mmDAGB0_DAGB_DLY_BASE_IDX 0 252 #define mmDAGB0_CNTL_MISC 0x0070 253 #define mmDAGB0_CNTL_MISC_BASE_IDX 0 254 #define mmDAGB0_CNTL_MISC2 0x0071 255 #define mmDAGB0_CNTL_MISC2_BASE_IDX 0 256 #define mmDAGB0_FIFO_EMPTY 0x0072 257 #define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 258 #define mmDAGB0_FIFO_FULL 0x0073 259 #define mmDAGB0_FIFO_FULL_BASE_IDX 0 260 #define mmDAGB0_WR_CREDITS_FULL 0x0074 261 #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 262 #define mmDAGB0_RD_CREDITS_FULL 0x0075 263 #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 264 #define mmDAGB0_PERFCOUNTER_LO 0x0076 265 #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 266 #define mmDAGB0_PERFCOUNTER_HI 0x0077 267 #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 268 #define mmDAGB0_PERFCOUNTER0_CFG 0x0078 269 #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 270 #define mmDAGB0_PERFCOUNTER1_CFG 0x0079 271 #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 272 #define mmDAGB0_PERFCOUNTER2_CFG 0x007a 273 #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 274 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x007b 275 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 276 #define mmDAGB0_RESERVE0 0x007c 277 #define mmDAGB0_RESERVE0_BASE_IDX 0 278 #define mmDAGB0_RESERVE1 0x007d 279 #define mmDAGB0_RESERVE1_BASE_IDX 0 280 #define mmDAGB0_RESERVE2 0x007e 281 #define mmDAGB0_RESERVE2_BASE_IDX 0 282 #define mmDAGB0_RESERVE3 0x007f 283 #define mmDAGB0_RESERVE3_BASE_IDX 0 284 #define mmDAGB0_RESERVE4 0x0080 285 #define mmDAGB0_RESERVE4_BASE_IDX 0 286 #define mmDAGB0_RESERVE5 0x0081 287 #define mmDAGB0_RESERVE5_BASE_IDX 0 288 #define mmDAGB0_RESERVE6 0x0082 289 #define mmDAGB0_RESERVE6_BASE_IDX 0 290 #define mmDAGB0_RESERVE7 0x0083 291 #define mmDAGB0_RESERVE7_BASE_IDX 0 292 #define mmDAGB0_RESERVE8 0x0084 293 #define mmDAGB0_RESERVE8_BASE_IDX 0 294 #define mmDAGB0_RESERVE9 0x0085 295 #define mmDAGB0_RESERVE9_BASE_IDX 0 296 #define mmDAGB0_RESERVE10 0x0086 297 #define mmDAGB0_RESERVE10_BASE_IDX 0 298 #define mmDAGB0_RESERVE11 0x0087 299 #define mmDAGB0_RESERVE11_BASE_IDX 0 300 #define mmDAGB0_RESERVE12 0x0088 301 #define mmDAGB0_RESERVE12_BASE_IDX 0 302 #define mmDAGB0_RESERVE13 0x0089 303 #define mmDAGB0_RESERVE13_BASE_IDX 0 304 #define mmDAGB0_RESERVE14 0x008a 305 #define mmDAGB0_RESERVE14_BASE_IDX 0 306 #define mmDAGB0_RESERVE15 0x008b 307 #define mmDAGB0_RESERVE15_BASE_IDX 0 308 #define mmDAGB0_RESERVE16 0x008c 309 #define mmDAGB0_RESERVE16_BASE_IDX 0 310 #define mmDAGB0_RESERVE17 0x008d 311 #define mmDAGB0_RESERVE17_BASE_IDX 0 312 #define mmDAGB0_RESERVE18 0x008e 313 #define mmDAGB0_RESERVE18_BASE_IDX 0 314 #define mmDAGB0_RESERVE19 0x008f 315 #define mmDAGB0_RESERVE19_BASE_IDX 0 316 #define mmDAGB0_RESERVE20 0x0090 317 #define mmDAGB0_RESERVE20_BASE_IDX 0 318 #define mmDAGB0_RESERVE21 0x0091 319 #define mmDAGB0_RESERVE21_BASE_IDX 0 320 #define mmDAGB0_RESERVE22 0x0092 321 #define mmDAGB0_RESERVE22_BASE_IDX 0 322 #define mmDAGB0_RESERVE23 0x0093 323 #define mmDAGB0_RESERVE23_BASE_IDX 0 324 #define mmDAGB0_RESERVE24 0x0094 325 #define mmDAGB0_RESERVE24_BASE_IDX 0 326 #define mmDAGB0_RESERVE25 0x0095 327 #define mmDAGB0_RESERVE25_BASE_IDX 0 328 #define mmDAGB0_RESERVE26 0x0096 329 #define mmDAGB0_RESERVE26_BASE_IDX 0 330 #define mmDAGB0_RESERVE27 0x0097 331 #define mmDAGB0_RESERVE27_BASE_IDX 0 332 #define mmDAGB0_RESERVE28 0x0098 333 #define mmDAGB0_RESERVE28_BASE_IDX 0 334 #define mmDAGB0_RESERVE29 0x0099 335 #define mmDAGB0_RESERVE29_BASE_IDX 0 336 #define mmDAGB0_RESERVE30 0x009a 337 #define mmDAGB0_RESERVE30_BASE_IDX 0 338 #define mmDAGB0_RESERVE31 0x009b 339 #define mmDAGB0_RESERVE31_BASE_IDX 0 340 #define mmDAGB0_RESERVE32 0x009c 341 #define mmDAGB0_RESERVE32_BASE_IDX 0 342 #define mmDAGB0_RESERVE33 0x009d 343 #define mmDAGB0_RESERVE33_BASE_IDX 0 344 #define mmDAGB0_RESERVE34 0x009e 345 #define mmDAGB0_RESERVE34_BASE_IDX 0 346 #define mmDAGB0_RESERVE35 0x009f 347 #define mmDAGB0_RESERVE35_BASE_IDX 0 348 #define mmDAGB0_RESERVE36 0x00a0 349 #define mmDAGB0_RESERVE36_BASE_IDX 0 350 #define mmDAGB0_RESERVE37 0x00a1 351 #define mmDAGB0_RESERVE37_BASE_IDX 0 352 #define mmDAGB0_RESERVE38 0x00a2 353 #define mmDAGB0_RESERVE38_BASE_IDX 0 354 #define mmDAGB0_RESERVE39 0x00a3 355 #define mmDAGB0_RESERVE39_BASE_IDX 0 356 #define mmDAGB0_RESERVE40 0x00a4 357 #define mmDAGB0_RESERVE40_BASE_IDX 0 358 #define mmDAGB0_RESERVE41 0x00a5 359 #define mmDAGB0_RESERVE41_BASE_IDX 0 360 #define mmDAGB0_RESERVE42 0x00a6 361 #define mmDAGB0_RESERVE42_BASE_IDX 0 362 #define mmDAGB0_RESERVE43 0x00a7 363 #define mmDAGB0_RESERVE43_BASE_IDX 0 364 #define mmDAGB0_RESERVE44 0x00a8 365 #define mmDAGB0_RESERVE44_BASE_IDX 0 366 #define mmDAGB0_RESERVE45 0x00a9 367 #define mmDAGB0_RESERVE45_BASE_IDX 0 368 #define mmDAGB0_RESERVE46 0x00aa 369 #define mmDAGB0_RESERVE46_BASE_IDX 0 370 #define mmDAGB0_RESERVE47 0x00ab 371 #define mmDAGB0_RESERVE47_BASE_IDX 0 372 #define mmDAGB0_RESERVE48 0x00ac 373 #define mmDAGB0_RESERVE48_BASE_IDX 0 374 #define mmDAGB0_RESERVE49 0x00ad 375 #define mmDAGB0_RESERVE49_BASE_IDX 0 376 #define mmDAGB0_RESERVE50 0x00ae 377 #define mmDAGB0_RESERVE50_BASE_IDX 0 378 #define mmDAGB0_RESERVE51 0x00af 379 #define mmDAGB0_RESERVE51_BASE_IDX 0 380 #define mmDAGB0_RESERVE52 0x00b0 381 #define mmDAGB0_RESERVE52_BASE_IDX 0 382 #define mmDAGB0_RESERVE53 0x00b1 383 #define mmDAGB0_RESERVE53_BASE_IDX 0 384 #define mmDAGB0_RESERVE54 0x00b2 385 #define mmDAGB0_RESERVE54_BASE_IDX 0 386 #define mmDAGB0_RESERVE55 0x00b3 387 #define mmDAGB0_RESERVE55_BASE_IDX 0 388 #define mmDAGB0_RESERVE56 0x00b4 389 #define mmDAGB0_RESERVE56_BASE_IDX 0 390 #define mmDAGB0_RESERVE57 0x00b5 391 #define mmDAGB0_RESERVE57_BASE_IDX 0 392 #define mmDAGB0_RESERVE58 0x00b6 393 #define mmDAGB0_RESERVE58_BASE_IDX 0 394 #define mmDAGB0_RESERVE59 0x00b7 395 #define mmDAGB0_RESERVE59_BASE_IDX 0 396 #define mmDAGB0_RESERVE60 0x00b8 397 #define mmDAGB0_RESERVE60_BASE_IDX 0 398 #define mmDAGB0_RESERVE61 0x00b9 399 #define mmDAGB0_RESERVE61_BASE_IDX 0 400 #define mmDAGB0_RESERVE62 0x00ba 401 #define mmDAGB0_RESERVE62_BASE_IDX 0 402 #define mmDAGB0_RESERVE63 0x00bb 403 #define mmDAGB0_RESERVE63_BASE_IDX 0 404 #define mmDAGB0_RESERVE64 0x00bc 405 #define mmDAGB0_RESERVE64_BASE_IDX 0 406 #define mmDAGB0_RESERVE65 0x00bd 407 #define mmDAGB0_RESERVE65_BASE_IDX 0 408 #define mmDAGB0_RESERVE66 0x00be 409 #define mmDAGB0_RESERVE66_BASE_IDX 0 410 #define mmDAGB0_RESERVE67 0x00bf 411 #define mmDAGB0_RESERVE67_BASE_IDX 0 412 #define mmDAGB0_RESERVE68 0x00c0 413 #define mmDAGB0_RESERVE68_BASE_IDX 0 414 #define mmDAGB0_RESERVE69 0x00c1 415 #define mmDAGB0_RESERVE69_BASE_IDX 0 416 #define mmDAGB0_RESERVE70 0x00c2 417 #define mmDAGB0_RESERVE70_BASE_IDX 0 418 #define mmDAGB0_RESERVE71 0x00c3 419 #define mmDAGB0_RESERVE71_BASE_IDX 0 420 #define mmDAGB0_RESERVE72 0x00c4 421 #define mmDAGB0_RESERVE72_BASE_IDX 0 422 #define mmDAGB0_RESERVE73 0x00c5 423 #define mmDAGB0_RESERVE73_BASE_IDX 0 424 #define mmDAGB0_RESERVE74 0x00c6 425 #define mmDAGB0_RESERVE74_BASE_IDX 0 426 #define mmDAGB0_RESERVE75 0x00c7 427 #define mmDAGB0_RESERVE75_BASE_IDX 0 428 #define mmDAGB0_RESERVE76 0x00c8 429 #define mmDAGB0_RESERVE76_BASE_IDX 0 430 #define mmDAGB0_RESERVE77 0x00c9 431 #define mmDAGB0_RESERVE77_BASE_IDX 0 432 #define mmDAGB0_RESERVE78 0x00ca 433 #define mmDAGB0_RESERVE78_BASE_IDX 0 434 #define mmDAGB0_RESERVE79 0x00cb 435 #define mmDAGB0_RESERVE79_BASE_IDX 0 436 #define mmDAGB0_RESERVE80 0x00cc 437 #define mmDAGB0_RESERVE80_BASE_IDX 0 438 #define mmDAGB0_RESERVE81 0x00cd 439 #define mmDAGB0_RESERVE81_BASE_IDX 0 440 #define mmDAGB0_RESERVE82 0x00ce 441 #define mmDAGB0_RESERVE82_BASE_IDX 0 442 #define mmDAGB0_RESERVE83 0x00cf 443 #define mmDAGB0_RESERVE83_BASE_IDX 0 444 #define mmDAGB0_RESERVE84 0x00d0 445 #define mmDAGB0_RESERVE84_BASE_IDX 0 446 #define mmDAGB0_RESERVE85 0x00d1 447 #define mmDAGB0_RESERVE85_BASE_IDX 0 448 #define mmDAGB0_RESERVE86 0x00d2 449 #define mmDAGB0_RESERVE86_BASE_IDX 0 450 #define mmDAGB0_RESERVE87 0x00d3 451 #define mmDAGB0_RESERVE87_BASE_IDX 0 452 #define mmDAGB0_RESERVE88 0x00d4 453 #define mmDAGB0_RESERVE88_BASE_IDX 0 454 #define mmDAGB0_RESERVE89 0x00d5 455 #define mmDAGB0_RESERVE89_BASE_IDX 0 456 #define mmDAGB0_RESERVE90 0x00d6 457 #define mmDAGB0_RESERVE90_BASE_IDX 0 458 #define mmDAGB0_RESERVE91 0x00d7 459 #define mmDAGB0_RESERVE91_BASE_IDX 0 460 #define mmDAGB0_RESERVE92 0x00d8 461 #define mmDAGB0_RESERVE92_BASE_IDX 0 462 #define mmDAGB0_RESERVE93 0x00d9 463 #define mmDAGB0_RESERVE93_BASE_IDX 0 464 #define mmDAGB0_RESERVE94 0x00da 465 #define mmDAGB0_RESERVE94_BASE_IDX 0 466 #define mmDAGB0_RESERVE95 0x00db 467 #define mmDAGB0_RESERVE95_BASE_IDX 0 468 #define mmDAGB0_RESERVE96 0x00dc 469 #define mmDAGB0_RESERVE96_BASE_IDX 0 470 #define mmDAGB0_RESERVE97 0x00dd 471 #define mmDAGB0_RESERVE97_BASE_IDX 0 472 #define mmDAGB0_RESERVE98 0x00de 473 #define mmDAGB0_RESERVE98_BASE_IDX 0 474 #define mmDAGB0_RESERVE99 0x00df 475 #define mmDAGB0_RESERVE99_BASE_IDX 0 476 #define mmDAGB0_RESERVE100 0x00e0 477 #define mmDAGB0_RESERVE100_BASE_IDX 0 478 #define mmDAGB0_RESERVE101 0x00e1 479 #define mmDAGB0_RESERVE101_BASE_IDX 0 480 #define mmDAGB0_RESERVE102 0x00e2 481 #define mmDAGB0_RESERVE102_BASE_IDX 0 482 #define mmDAGB0_RESERVE103 0x00e3 483 #define mmDAGB0_RESERVE103_BASE_IDX 0 484 #define mmDAGB0_RESERVE104 0x00e4 485 #define mmDAGB0_RESERVE104_BASE_IDX 0 486 #define mmDAGB0_RESERVE105 0x00e5 487 #define mmDAGB0_RESERVE105_BASE_IDX 0 488 #define mmDAGB0_RESERVE106 0x00e6 489 #define mmDAGB0_RESERVE106_BASE_IDX 0 490 #define mmDAGB0_RESERVE107 0x00e7 491 #define mmDAGB0_RESERVE107_BASE_IDX 0 492 #define mmDAGB0_RESERVE108 0x00e8 493 #define mmDAGB0_RESERVE108_BASE_IDX 0 494 #define mmDAGB0_RESERVE109 0x00e9 495 #define mmDAGB0_RESERVE109_BASE_IDX 0 496 #define mmDAGB0_RESERVE110 0x00ea 497 #define mmDAGB0_RESERVE110_BASE_IDX 0 498 #define mmDAGB0_RESERVE111 0x00eb 499 #define mmDAGB0_RESERVE111_BASE_IDX 0 500 #define mmDAGB0_RESERVE112 0x00ec 501 #define mmDAGB0_RESERVE112_BASE_IDX 0 502 #define mmDAGB0_RESERVE113 0x00ed 503 #define mmDAGB0_RESERVE113_BASE_IDX 0 504 #define mmDAGB0_RESERVE114 0x00ee 505 #define mmDAGB0_RESERVE114_BASE_IDX 0 506 #define mmDAGB0_RESERVE115 0x00ef 507 #define mmDAGB0_RESERVE115_BASE_IDX 0 508 #define mmDAGB0_RESERVE116 0x00f0 509 #define mmDAGB0_RESERVE116_BASE_IDX 0 510 #define mmDAGB0_RESERVE117 0x00f1 511 #define mmDAGB0_RESERVE117_BASE_IDX 0 512 #define mmDAGB0_RESERVE118 0x00f2 513 #define mmDAGB0_RESERVE118_BASE_IDX 0 514 #define mmDAGB0_RESERVE119 0x00f3 515 #define mmDAGB0_RESERVE119_BASE_IDX 0 516 #define mmDAGB0_RESERVE120 0x00f4 517 #define mmDAGB0_RESERVE120_BASE_IDX 0 518 #define mmDAGB0_RESERVE121 0x00f5 519 #define mmDAGB0_RESERVE121_BASE_IDX 0 520 #define mmDAGB0_RESERVE122 0x00f6 521 #define mmDAGB0_RESERVE122_BASE_IDX 0 522 #define mmDAGB0_RESERVE123 0x00f7 523 #define mmDAGB0_RESERVE123_BASE_IDX 0 524 #define mmDAGB0_RESERVE124 0x00f8 525 #define mmDAGB0_RESERVE124_BASE_IDX 0 526 #define mmDAGB0_RESERVE125 0x00f9 527 #define mmDAGB0_RESERVE125_BASE_IDX 0 528 #define mmDAGB0_RESERVE126 0x00fa 529 #define mmDAGB0_RESERVE126_BASE_IDX 0 530 #define mmDAGB0_RESERVE127 0x00fb 531 #define mmDAGB0_RESERVE127_BASE_IDX 0 532 #define mmDAGB0_RESERVE128 0x00fc 533 #define mmDAGB0_RESERVE128_BASE_IDX 0 534 #define mmDAGB0_RESERVE129 0x00fd 535 #define mmDAGB0_RESERVE129_BASE_IDX 0 536 #define mmDAGB0_RESERVE130 0x00fe 537 #define mmDAGB0_RESERVE130_BASE_IDX 0 538 #define mmDAGB0_RESERVE131 0x00ff 539 #define mmDAGB0_RESERVE131_BASE_IDX 0 540 541 542 // addressBlock: mmhub_mmea_mmeadec 543 // base address: 0x68400 544 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 545 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 546 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 547 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 548 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 549 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 550 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 551 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 552 #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 553 #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 554 #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 555 #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 556 #define mmMMEA0_DRAM_RD_LAZY 0x0106 557 #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 558 #define mmMMEA0_DRAM_WR_LAZY 0x0107 559 #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 560 #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 561 #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 562 #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 563 #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 564 #define mmMMEA0_DRAM_PAGE_BURST 0x010a 565 #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 566 #define mmMMEA0_DRAM_RD_PRI_AGE 0x010b 567 #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 568 #define mmMMEA0_DRAM_WR_PRI_AGE 0x010c 569 #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 570 #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d 571 #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 572 #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e 573 #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 574 #define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f 575 #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 576 #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 577 #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 578 #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 579 #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 580 #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 581 #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 582 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 583 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 584 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 585 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 586 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 587 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 588 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 589 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 590 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 591 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 592 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 593 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 594 #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 595 #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 596 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 597 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 598 #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 599 #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 600 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 601 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 602 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 603 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 604 #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 605 #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 606 #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145 607 #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 608 #define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 609 #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 610 #define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 611 #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 612 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 613 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 614 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a 615 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 616 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b 617 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 618 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c 619 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 620 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d 621 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 622 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e 623 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 624 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f 625 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 626 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150 627 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 628 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151 629 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 630 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152 631 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 632 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0153 633 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 0 634 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0154 635 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 0 636 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0155 637 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 0 638 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0156 639 #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 0 640 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0165 641 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 642 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0166 643 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 644 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0167 645 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 646 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0168 647 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 648 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0169 649 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 650 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016a 651 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 652 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016b 653 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 654 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016c 655 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 656 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016d 657 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 658 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x016e 659 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 660 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x016f 661 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 662 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0170 663 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 664 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0171 665 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 666 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0172 667 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 668 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0173 669 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 670 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0174 671 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 672 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0175 673 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 674 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0176 675 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 676 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0177 677 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 678 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0178 679 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 680 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0179 681 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 682 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017a 683 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 684 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x017b 685 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 686 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x017c 687 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 688 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x017d 689 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 690 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x017e 691 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 692 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x017f 693 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 694 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0180 695 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 696 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0181 697 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 698 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0182 699 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 700 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0183 701 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 702 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0184 703 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 704 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0185 705 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 706 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0186 707 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 708 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0187 709 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 710 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0188 711 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 712 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0189 713 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 714 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018a 715 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 716 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018b 717 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 718 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x018c 719 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 720 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x018d 721 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 722 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x018e 723 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 724 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x018f 725 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 726 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0190 727 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 728 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0191 729 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 730 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0192 731 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 732 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0193 733 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 734 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0194 735 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 736 #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd 737 #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 738 #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de 739 #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 740 #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df 741 #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 742 #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0 743 #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 744 #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1 745 #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 746 #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2 747 #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 748 #define mmMMEA0_IO_GROUP_BURST 0x01e3 749 #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 750 #define mmMMEA0_IO_RD_PRI_AGE 0x01e4 751 #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 752 #define mmMMEA0_IO_WR_PRI_AGE 0x01e5 753 #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 754 #define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6 755 #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 756 #define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7 757 #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 758 #define mmMMEA0_IO_RD_PRI_FIXED 0x01e8 759 #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 760 #define mmMMEA0_IO_WR_PRI_FIXED 0x01e9 761 #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 762 #define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea 763 #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 764 #define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb 765 #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 766 #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec 767 #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 768 #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed 769 #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 770 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee 771 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 772 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef 773 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 774 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0 775 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 776 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1 777 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 778 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2 779 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 780 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3 781 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 782 #define mmMMEA0_SDP_ARB_DRAM 0x01f4 783 #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 784 #define mmMMEA0_SDP_ARB_FINAL 0x01f6 785 #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 786 #define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7 787 #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 788 #define mmMMEA0_SDP_IO_PRIORITY 0x01f9 789 #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 790 #define mmMMEA0_SDP_CREDITS 0x01fa 791 #define mmMMEA0_SDP_CREDITS_BASE_IDX 0 792 #define mmMMEA0_SDP_TAG_RESERVE0 0x01fb 793 #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 794 #define mmMMEA0_SDP_TAG_RESERVE1 0x01fc 795 #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 796 #define mmMMEA0_SDP_VCC_RESERVE0 0x01fd 797 #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 798 #define mmMMEA0_SDP_VCC_RESERVE1 0x01fe 799 #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 800 #define mmMMEA0_SDP_VCD_RESERVE0 0x01ff 801 #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 802 #define mmMMEA0_SDP_VCD_RESERVE1 0x0200 803 #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 804 #define mmMMEA0_SDP_REQ_CNTL 0x0201 805 #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 806 #define mmMMEA0_MISC 0x0202 807 #define mmMMEA0_MISC_BASE_IDX 0 808 #define mmMMEA0_LATENCY_SAMPLING 0x0203 809 #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 810 #define mmMMEA0_PERFCOUNTER_LO 0x0204 811 #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 812 #define mmMMEA0_PERFCOUNTER_HI 0x0205 813 #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 814 #define mmMMEA0_PERFCOUNTER0_CFG 0x0206 815 #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 816 #define mmMMEA0_PERFCOUNTER1_CFG 0x0207 817 #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 818 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208 819 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 820 #define mmMMEA0_EDC_CNT 0x020f 821 #define mmMMEA0_EDC_CNT_BASE_IDX 0 822 #define mmMMEA0_EDC_CNT2 0x0210 823 #define mmMMEA0_EDC_CNT2_BASE_IDX 0 824 #define mmMMEA0_DSM_CNTL 0x0211 825 #define mmMMEA0_DSM_CNTL_BASE_IDX 0 826 #define mmMMEA0_DSM_CNTLA 0x0212 827 #define mmMMEA0_DSM_CNTLA_BASE_IDX 0 828 #define mmMMEA0_DSM_CNTLB 0x0213 829 #define mmMMEA0_DSM_CNTLB_BASE_IDX 0 830 #define mmMMEA0_DSM_CNTL2 0x0214 831 #define mmMMEA0_DSM_CNTL2_BASE_IDX 0 832 #define mmMMEA0_DSM_CNTL2A 0x0215 833 #define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 834 #define mmMMEA0_DSM_CNTL2B 0x0216 835 #define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 836 #define mmMMEA0_CGTT_CLK_CTRL 0x0218 837 #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 838 #define mmMMEA0_EDC_MODE 0x0219 839 #define mmMMEA0_EDC_MODE_BASE_IDX 0 840 #define mmMMEA0_ERR_STATUS 0x021a 841 #define mmMMEA0_ERR_STATUS_BASE_IDX 0 842 #define mmMMEA0_MISC2 0x021b 843 #define mmMMEA0_MISC2_BASE_IDX 0 844 #define mmMMEA0_ADDRDEC_SELECT 0x021c 845 #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 0 846 847 848 // addressBlock: mmhub_pctldec 849 // base address: 0x68e00 850 #define mmPCTL_MISC 0x0380 851 #define mmPCTL_MISC_BASE_IDX 0 852 #define mmPCTL_MMHUB_DEEPSLEEP 0x0381 853 #define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 854 #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 855 #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 856 #define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 857 #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 858 #define mmPCTL_PG_DAGB 0x0384 859 #define mmPCTL_PG_DAGB_BASE_IDX 0 860 #define mmPCTL0_RENG_RAM_INDEX 0x0385 861 #define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 862 #define mmPCTL0_RENG_RAM_DATA 0x0386 863 #define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 864 #define mmPCTL0_RENG_EXECUTE 0x0387 865 #define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 866 #define mmPCTL1_RENG_RAM_INDEX 0x0388 867 #define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 868 #define mmPCTL1_RENG_RAM_DATA 0x0389 869 #define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 870 #define mmPCTL1_RENG_EXECUTE 0x038a 871 #define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 872 #define mmPCTL2_RENG_RAM_INDEX 0x038b 873 #define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 874 #define mmPCTL2_RENG_RAM_DATA 0x038c 875 #define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 876 #define mmPCTL2_RENG_EXECUTE 0x038d 877 #define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 878 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x038e 879 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 880 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038f 881 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 882 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x0390 883 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 884 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x0391 885 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 886 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x0392 887 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 888 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x0393 889 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 890 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0394 891 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 892 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0395 893 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 894 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0396 895 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 896 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0397 897 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 898 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0398 899 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 900 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0399 901 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 902 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x039a 903 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 904 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039b 905 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 906 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039c 907 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 908 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039d 909 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 910 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039e 911 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 912 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x039f 913 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 914 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a0 915 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 916 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a1 917 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 918 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a2 919 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 920 #define mmPCTL0_MISC 0x03a3 921 #define mmPCTL0_MISC_BASE_IDX 0 922 #define mmPCTL1_MISC 0x03a4 923 #define mmPCTL1_MISC_BASE_IDX 0 924 #define mmPCTL2_MISC 0x03a5 925 #define mmPCTL2_MISC_BASE_IDX 0 926 #define mmPCTL_PERFCOUNTER_LO 0x03a6 927 #define mmPCTL_PERFCOUNTER_LO_BASE_IDX 0 928 #define mmPCTL_PERFCOUNTER_HI 0x03a7 929 #define mmPCTL_PERFCOUNTER_HI_BASE_IDX 0 930 #define mmPCTL_PERFCOUNTER0_CFG 0x03a8 931 #define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 932 #define mmPCTL_PERFCOUNTER1_CFG 0x03a9 933 #define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 934 #define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03aa 935 #define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 936 937 938 // addressBlock: mmhub_l1tlb_mmvml1pfdec 939 // base address: 0x69600 940 #define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588 941 #define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 942 #define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589 943 #define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 944 #define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a 945 #define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 946 #define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b 947 #define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 948 #define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c 949 #define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 950 #define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d 951 #define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 952 #define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e 953 #define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 954 #define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f 955 #define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 956 957 958 // addressBlock: mmhub_l1tlb_mmvml1pldec 959 // base address: 0x69650 960 #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 961 #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 962 #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 963 #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 964 #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 965 #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 966 #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 967 #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 968 #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 969 #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 970 971 972 // addressBlock: mmhub_l1tlb_mmvml1prdec 973 // base address: 0x69670 974 #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x059c 975 #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 976 #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x059d 977 #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 978 979 980 // addressBlock: mmhub_mmutcl2_mmatcl2dec 981 // base address: 0x69900 982 #define mmMM_ATC_L2_CNTL 0x0640 983 #define mmMM_ATC_L2_CNTL_BASE_IDX 0 984 #define mmMM_ATC_L2_CNTL2 0x0641 985 #define mmMM_ATC_L2_CNTL2_BASE_IDX 0 986 #define mmMM_ATC_L2_CACHE_DATA0 0x0644 987 #define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 0 988 #define mmMM_ATC_L2_CACHE_DATA1 0x0645 989 #define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 0 990 #define mmMM_ATC_L2_CACHE_DATA2 0x0646 991 #define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 0 992 #define mmMM_ATC_L2_CNTL3 0x0647 993 #define mmMM_ATC_L2_CNTL3_BASE_IDX 0 994 #define mmMM_ATC_L2_STATUS 0x0648 995 #define mmMM_ATC_L2_STATUS_BASE_IDX 0 996 #define mmMM_ATC_L2_STATUS2 0x0649 997 #define mmMM_ATC_L2_STATUS2_BASE_IDX 0 998 #define mmMM_ATC_L2_MISC_CG 0x064a 999 #define mmMM_ATC_L2_MISC_CG_BASE_IDX 0 1000 #define mmMM_ATC_L2_MEM_POWER_LS 0x064b 1001 #define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0 1002 #define mmMM_ATC_L2_CGTT_CLK_CTRL 0x064c 1003 #define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1004 #define mmMM_ATC_L2_SDPPORT_CTRL 0x064d 1005 #define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0 1006 1007 1008 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 1009 // base address: 0x69a00 1010 #define mmMMVM_L2_CNTL 0x0680 1011 #define mmMMVM_L2_CNTL_BASE_IDX 0 1012 #define mmMMVM_L2_CNTL2 0x0681 1013 #define mmMMVM_L2_CNTL2_BASE_IDX 0 1014 #define mmMMVM_L2_CNTL3 0x0682 1015 #define mmMMVM_L2_CNTL3_BASE_IDX 0 1016 #define mmMMVM_L2_STATUS 0x0683 1017 #define mmMMVM_L2_STATUS_BASE_IDX 0 1018 #define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0684 1019 #define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1020 #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 1021 #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1022 #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 1023 #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1024 #define mmMMVM_INVALIDATE_CNTL 0x0687 1025 #define mmMMVM_INVALIDATE_CNTL_BASE_IDX 0 1026 #define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0688 1027 #define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1028 #define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0689 1029 #define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1030 #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x068a 1031 #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1032 #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068b 1033 #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1034 #define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x068c 1035 #define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1036 #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068d 1037 #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1038 #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068e 1039 #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1040 #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068f 1041 #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1042 #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0690 1043 #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1044 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0692 1045 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1046 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0693 1047 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1048 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0694 1049 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1050 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0695 1051 #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1052 #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0696 1053 #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1054 #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0697 1055 #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1056 #define mmMMVM_L2_CNTL4 0x0698 1057 #define mmMMVM_L2_CNTL4_BASE_IDX 0 1058 #define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0699 1059 #define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1060 #define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x069a 1061 #define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1062 #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x069b 1063 #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1064 #define mmMMVM_L2_CACHE_PARITY_CNTL 0x069c 1065 #define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1066 #define mmMMVM_L2_IH_LOG_CNTL 0x069d 1067 #define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 0 1068 #define mmMMVM_L2_IH_LOG_BUSY 0x069e 1069 #define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 0 1070 #define mmMMVM_L2_CGTT_CLK_CTRL 0x069f 1071 #define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1072 #define mmMMVM_L2_CNTL5 0x06a1 1073 #define mmMMVM_L2_CNTL5_BASE_IDX 0 1074 #define mmMMVM_L2_GCR_CNTL 0x06a2 1075 #define mmMMVM_L2_GCR_CNTL_BASE_IDX 0 1076 #define mmMMVML2_WALKER_MACRO_THROTTLE_TIME 0x06a3 1077 #define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 1078 #define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x06a4 1079 #define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 1080 #define mmMMVML2_WALKER_MICRO_THROTTLE_TIME 0x06a5 1081 #define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 1082 #define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x06a6 1083 #define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 1084 1085 1086 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 1087 // base address: 0x69b00 1088 #define mmMMVM_CONTEXT0_CNTL 0x06c0 1089 #define mmMMVM_CONTEXT0_CNTL_BASE_IDX 0 1090 #define mmMMVM_CONTEXT1_CNTL 0x06c1 1091 #define mmMMVM_CONTEXT1_CNTL_BASE_IDX 0 1092 #define mmMMVM_CONTEXT2_CNTL 0x06c2 1093 #define mmMMVM_CONTEXT2_CNTL_BASE_IDX 0 1094 #define mmMMVM_CONTEXT3_CNTL 0x06c3 1095 #define mmMMVM_CONTEXT3_CNTL_BASE_IDX 0 1096 #define mmMMVM_CONTEXT4_CNTL 0x06c4 1097 #define mmMMVM_CONTEXT4_CNTL_BASE_IDX 0 1098 #define mmMMVM_CONTEXT5_CNTL 0x06c5 1099 #define mmMMVM_CONTEXT5_CNTL_BASE_IDX 0 1100 #define mmMMVM_CONTEXT6_CNTL 0x06c6 1101 #define mmMMVM_CONTEXT6_CNTL_BASE_IDX 0 1102 #define mmMMVM_CONTEXT7_CNTL 0x06c7 1103 #define mmMMVM_CONTEXT7_CNTL_BASE_IDX 0 1104 #define mmMMVM_CONTEXT8_CNTL 0x06c8 1105 #define mmMMVM_CONTEXT8_CNTL_BASE_IDX 0 1106 #define mmMMVM_CONTEXT9_CNTL 0x06c9 1107 #define mmMMVM_CONTEXT9_CNTL_BASE_IDX 0 1108 #define mmMMVM_CONTEXT10_CNTL 0x06ca 1109 #define mmMMVM_CONTEXT10_CNTL_BASE_IDX 0 1110 #define mmMMVM_CONTEXT11_CNTL 0x06cb 1111 #define mmMMVM_CONTEXT11_CNTL_BASE_IDX 0 1112 #define mmMMVM_CONTEXT12_CNTL 0x06cc 1113 #define mmMMVM_CONTEXT12_CNTL_BASE_IDX 0 1114 #define mmMMVM_CONTEXT13_CNTL 0x06cd 1115 #define mmMMVM_CONTEXT13_CNTL_BASE_IDX 0 1116 #define mmMMVM_CONTEXT14_CNTL 0x06ce 1117 #define mmMMVM_CONTEXT14_CNTL_BASE_IDX 0 1118 #define mmMMVM_CONTEXT15_CNTL 0x06cf 1119 #define mmMMVM_CONTEXT15_CNTL_BASE_IDX 0 1120 #define mmMMVM_CONTEXTS_DISABLE 0x06d0 1121 #define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 0 1122 #define mmMMVM_INVALIDATE_ENG0_SEM 0x06d1 1123 #define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1124 #define mmMMVM_INVALIDATE_ENG1_SEM 0x06d2 1125 #define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1126 #define mmMMVM_INVALIDATE_ENG2_SEM 0x06d3 1127 #define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1128 #define mmMMVM_INVALIDATE_ENG3_SEM 0x06d4 1129 #define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1130 #define mmMMVM_INVALIDATE_ENG4_SEM 0x06d5 1131 #define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1132 #define mmMMVM_INVALIDATE_ENG5_SEM 0x06d6 1133 #define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1134 #define mmMMVM_INVALIDATE_ENG6_SEM 0x06d7 1135 #define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1136 #define mmMMVM_INVALIDATE_ENG7_SEM 0x06d8 1137 #define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1138 #define mmMMVM_INVALIDATE_ENG8_SEM 0x06d9 1139 #define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1140 #define mmMMVM_INVALIDATE_ENG9_SEM 0x06da 1141 #define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1142 #define mmMMVM_INVALIDATE_ENG10_SEM 0x06db 1143 #define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1144 #define mmMMVM_INVALIDATE_ENG11_SEM 0x06dc 1145 #define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1146 #define mmMMVM_INVALIDATE_ENG12_SEM 0x06dd 1147 #define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1148 #define mmMMVM_INVALIDATE_ENG13_SEM 0x06de 1149 #define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1150 #define mmMMVM_INVALIDATE_ENG14_SEM 0x06df 1151 #define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1152 #define mmMMVM_INVALIDATE_ENG15_SEM 0x06e0 1153 #define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1154 #define mmMMVM_INVALIDATE_ENG16_SEM 0x06e1 1155 #define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1156 #define mmMMVM_INVALIDATE_ENG17_SEM 0x06e2 1157 #define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1158 #define mmMMVM_INVALIDATE_ENG0_REQ 0x06e3 1159 #define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1160 #define mmMMVM_INVALIDATE_ENG1_REQ 0x06e4 1161 #define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1162 #define mmMMVM_INVALIDATE_ENG2_REQ 0x06e5 1163 #define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1164 #define mmMMVM_INVALIDATE_ENG3_REQ 0x06e6 1165 #define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1166 #define mmMMVM_INVALIDATE_ENG4_REQ 0x06e7 1167 #define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1168 #define mmMMVM_INVALIDATE_ENG5_REQ 0x06e8 1169 #define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1170 #define mmMMVM_INVALIDATE_ENG6_REQ 0x06e9 1171 #define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1172 #define mmMMVM_INVALIDATE_ENG7_REQ 0x06ea 1173 #define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1174 #define mmMMVM_INVALIDATE_ENG8_REQ 0x06eb 1175 #define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1176 #define mmMMVM_INVALIDATE_ENG9_REQ 0x06ec 1177 #define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1178 #define mmMMVM_INVALIDATE_ENG10_REQ 0x06ed 1179 #define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1180 #define mmMMVM_INVALIDATE_ENG11_REQ 0x06ee 1181 #define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1182 #define mmMMVM_INVALIDATE_ENG12_REQ 0x06ef 1183 #define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1184 #define mmMMVM_INVALIDATE_ENG13_REQ 0x06f0 1185 #define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1186 #define mmMMVM_INVALIDATE_ENG14_REQ 0x06f1 1187 #define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1188 #define mmMMVM_INVALIDATE_ENG15_REQ 0x06f2 1189 #define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1190 #define mmMMVM_INVALIDATE_ENG16_REQ 0x06f3 1191 #define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1192 #define mmMMVM_INVALIDATE_ENG17_REQ 0x06f4 1193 #define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1194 #define mmMMVM_INVALIDATE_ENG0_ACK 0x06f5 1195 #define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1196 #define mmMMVM_INVALIDATE_ENG1_ACK 0x06f6 1197 #define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1198 #define mmMMVM_INVALIDATE_ENG2_ACK 0x06f7 1199 #define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1200 #define mmMMVM_INVALIDATE_ENG3_ACK 0x06f8 1201 #define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1202 #define mmMMVM_INVALIDATE_ENG4_ACK 0x06f9 1203 #define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1204 #define mmMMVM_INVALIDATE_ENG5_ACK 0x06fa 1205 #define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1206 #define mmMMVM_INVALIDATE_ENG6_ACK 0x06fb 1207 #define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1208 #define mmMMVM_INVALIDATE_ENG7_ACK 0x06fc 1209 #define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1210 #define mmMMVM_INVALIDATE_ENG8_ACK 0x06fd 1211 #define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1212 #define mmMMVM_INVALIDATE_ENG9_ACK 0x06fe 1213 #define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1214 #define mmMMVM_INVALIDATE_ENG10_ACK 0x06ff 1215 #define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1216 #define mmMMVM_INVALIDATE_ENG11_ACK 0x0700 1217 #define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1218 #define mmMMVM_INVALIDATE_ENG12_ACK 0x0701 1219 #define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1220 #define mmMMVM_INVALIDATE_ENG13_ACK 0x0702 1221 #define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1222 #define mmMMVM_INVALIDATE_ENG14_ACK 0x0703 1223 #define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1224 #define mmMMVM_INVALIDATE_ENG15_ACK 0x0704 1225 #define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1226 #define mmMMVM_INVALIDATE_ENG16_ACK 0x0705 1227 #define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1228 #define mmMMVM_INVALIDATE_ENG17_ACK 0x0706 1229 #define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1230 #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 1231 #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1232 #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 1233 #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1234 #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 1235 #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1236 #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a 1237 #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1238 #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b 1239 #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1240 #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c 1241 #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1242 #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d 1243 #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1244 #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e 1245 #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1246 #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f 1247 #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1248 #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 1249 #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1250 #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 1251 #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1252 #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 1253 #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1254 #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 1255 #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1256 #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 1257 #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1258 #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 1259 #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1260 #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 1261 #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1262 #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 1263 #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1264 #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 1265 #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1266 #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 1267 #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1268 #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a 1269 #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1270 #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b 1271 #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1272 #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c 1273 #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1274 #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d 1275 #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1276 #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e 1277 #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1278 #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f 1279 #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1280 #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 1281 #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1282 #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 1283 #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1284 #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 1285 #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1286 #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 1287 #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1288 #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 1289 #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1290 #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 1291 #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1292 #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 1293 #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1294 #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 1295 #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1296 #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 1297 #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1298 #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 1299 #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1300 #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a 1301 #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1302 #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 1303 #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1304 #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 1305 #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1306 #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d 1307 #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1308 #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e 1309 #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1310 #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f 1311 #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1312 #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 1313 #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1314 #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 1315 #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1316 #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 1317 #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1318 #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 1319 #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1320 #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 1321 #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1322 #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 1323 #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1324 #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 1325 #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1326 #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 1327 #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1328 #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 1329 #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1330 #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 1331 #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1332 #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a 1333 #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1334 #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b 1335 #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1336 #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c 1337 #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1338 #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d 1339 #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1340 #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e 1341 #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1342 #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f 1343 #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1344 #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 1345 #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1346 #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 1347 #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1348 #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 1349 #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1350 #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 1351 #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1352 #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 1353 #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1354 #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 1355 #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1356 #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 1357 #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1358 #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 1359 #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1360 #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 1361 #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1362 #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 1363 #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1364 #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a 1365 #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1366 #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 1367 #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1368 #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 1369 #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1370 #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d 1371 #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1372 #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e 1373 #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1374 #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f 1375 #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1376 #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 1377 #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1378 #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 1379 #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1380 #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 1381 #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1382 #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 1383 #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1384 #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 1385 #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1386 #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 1387 #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1388 #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 1389 #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1390 #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 1391 #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1392 #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 1393 #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1394 #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 1395 #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1396 #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a 1397 #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1398 #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b 1399 #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1400 #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c 1401 #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1402 #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d 1403 #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1404 #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e 1405 #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1406 #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f 1407 #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1408 #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 1409 #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1410 #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 1411 #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1412 #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 1413 #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1414 #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 1415 #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1416 #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 1417 #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1418 #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 1419 #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1420 #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 1421 #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1422 #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 1423 #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1424 #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 1425 #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1426 #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 1427 #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1428 #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a 1429 #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1430 #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 1431 #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1432 #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 1433 #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1434 #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d 1435 #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1436 #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e 1437 #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1438 #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f 1439 #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1440 #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 1441 #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1442 #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 1443 #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1444 #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 1445 #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1446 #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 1447 #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1448 #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 1449 #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1450 #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 1451 #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1452 #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 1453 #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1454 #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 1455 #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1456 #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 1457 #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1458 #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 1459 #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1460 #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a 1461 #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1462 #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b 1463 #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1464 #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c 1465 #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1466 #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d 1467 #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1468 #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e 1469 #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1470 #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f 1471 #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1472 #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 1473 #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1474 #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 1475 #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1476 #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 1477 #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1478 #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 1479 #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1480 #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 1481 #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1482 #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 1483 #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1484 #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 1485 #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1486 #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 1487 #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1488 #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 1489 #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1490 #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 1491 #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1492 #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a 1493 #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1494 1495 1496 // addressBlock: mmhub_mmutcl2_mmvml2pldec 1497 // base address: 0x69e90 1498 #define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 1499 #define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1500 #define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 1501 #define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1502 #define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 1503 #define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 1504 #define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 1505 #define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 1506 #define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 1507 #define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 1508 #define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 1509 #define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 1510 #define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x07aa 1511 #define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 1512 #define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x07ab 1513 #define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 1514 #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac 1515 #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1516 1517 1518 // addressBlock: mmhub_mmutcl2_mmvml2prdec 1519 // base address: 0x69ee0 1520 #define mmMMMC_VM_L2_PERFCOUNTER_LO 0x07b8 1521 #define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 1522 #define mmMMMC_VM_L2_PERFCOUNTER_HI 0x07b9 1523 #define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 1524 1525 1526 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1527 // base address: 0x69f30 1528 #define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x07cc 1529 #define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 1530 #define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x07cd 1531 #define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 1532 #define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x07ce 1533 #define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 1534 #define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x07cf 1535 #define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 1536 #define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 1537 #define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 1538 #define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 1539 #define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 1540 #define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 1541 #define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 1542 #define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 1543 #define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 1544 #define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 1545 #define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 1546 #define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 1547 #define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 1548 #define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 1549 #define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 1550 #define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 1551 #define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 1552 #define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 1553 #define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 1554 #define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 1555 #define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 1556 #define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x07da 1557 #define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 1558 #define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x07db 1559 #define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 1560 #define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x07dc 1561 #define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 0 1562 #define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x07dd 1563 #define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 0 1564 #define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x07de 1565 #define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 0 1566 #define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x07df 1567 #define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 0 1568 #define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x07e0 1569 #define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 0 1570 #define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x07e1 1571 #define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 0 1572 #define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x07e2 1573 #define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 0 1574 #define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x07e3 1575 #define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 0 1576 #define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x07e4 1577 #define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 0 1578 #define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x07e5 1579 #define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 0 1580 #define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x07e6 1581 #define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 0 1582 #define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x07e7 1583 #define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 0 1584 #define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x07e8 1585 #define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 0 1586 #define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x07e9 1587 #define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 0 1588 #define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x07ea 1589 #define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 0 1590 #define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x07eb 1591 #define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 0 1592 #define mmMMVM_IOMMU_MMIO_CNTRL_1 0x07ec 1593 #define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 1594 #define mmMMMC_VM_MARC_BASE_LO_0 0x07ed 1595 #define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 0 1596 #define mmMMMC_VM_MARC_BASE_LO_1 0x07ee 1597 #define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 0 1598 #define mmMMMC_VM_MARC_BASE_LO_2 0x07ef 1599 #define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 0 1600 #define mmMMMC_VM_MARC_BASE_LO_3 0x07f0 1601 #define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 0 1602 #define mmMMMC_VM_MARC_BASE_HI_0 0x07f1 1603 #define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 0 1604 #define mmMMMC_VM_MARC_BASE_HI_1 0x07f2 1605 #define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 0 1606 #define mmMMMC_VM_MARC_BASE_HI_2 0x07f3 1607 #define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 0 1608 #define mmMMMC_VM_MARC_BASE_HI_3 0x07f4 1609 #define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 0 1610 #define mmMMMC_VM_MARC_RELOC_LO_0 0x07f5 1611 #define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 1612 #define mmMMMC_VM_MARC_RELOC_LO_1 0x07f6 1613 #define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 1614 #define mmMMMC_VM_MARC_RELOC_LO_2 0x07f7 1615 #define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 1616 #define mmMMMC_VM_MARC_RELOC_LO_3 0x07f8 1617 #define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 1618 #define mmMMMC_VM_MARC_RELOC_HI_0 0x07f9 1619 #define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 1620 #define mmMMMC_VM_MARC_RELOC_HI_1 0x07fa 1621 #define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 1622 #define mmMMMC_VM_MARC_RELOC_HI_2 0x07fb 1623 #define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 1624 #define mmMMMC_VM_MARC_RELOC_HI_3 0x07fc 1625 #define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 1626 #define mmMMMC_VM_MARC_LEN_LO_0 0x07fd 1627 #define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 0 1628 #define mmMMMC_VM_MARC_LEN_LO_1 0x07fe 1629 #define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 0 1630 #define mmMMMC_VM_MARC_LEN_LO_2 0x07ff 1631 #define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 0 1632 #define mmMMMC_VM_MARC_LEN_LO_3 0x0800 1633 #define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 0 1634 #define mmMMMC_VM_MARC_LEN_HI_0 0x0801 1635 #define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 0 1636 #define mmMMMC_VM_MARC_LEN_HI_1 0x0802 1637 #define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 0 1638 #define mmMMMC_VM_MARC_LEN_HI_2 0x0803 1639 #define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 0 1640 #define mmMMMC_VM_MARC_LEN_HI_3 0x0804 1641 #define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 0 1642 #define mmMMVM_IOMMU_CONTROL_REGISTER 0x0805 1643 #define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 1644 #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0806 1645 #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 1646 #define mmMMVM_PCIE_ATS_CNTL 0x0807 1647 #define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 0 1648 #define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0808 1649 #define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 1650 #define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0809 1651 #define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 1652 #define mmMMVM_PCIE_ATS_CNTL_VF_2 0x080a 1653 #define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 1654 #define mmMMVM_PCIE_ATS_CNTL_VF_3 0x080b 1655 #define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 1656 #define mmMMVM_PCIE_ATS_CNTL_VF_4 0x080c 1657 #define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 1658 #define mmMMVM_PCIE_ATS_CNTL_VF_5 0x080d 1659 #define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 1660 #define mmMMVM_PCIE_ATS_CNTL_VF_6 0x080e 1661 #define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 1662 #define mmMMVM_PCIE_ATS_CNTL_VF_7 0x080f 1663 #define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 1664 #define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0810 1665 #define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 1666 #define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0811 1667 #define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 1668 #define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0812 1669 #define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 1670 #define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0813 1671 #define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 1672 #define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0814 1673 #define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 1674 #define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0815 1675 #define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 1676 #define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0816 1677 #define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 1678 #define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0817 1679 #define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 1680 #define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0818 1681 #define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 0 1682 #define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0819 1683 #define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 0 1684 #define mmMMVM_PCIE_ATS_CNTL_VF_18 0x081a 1685 #define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 0 1686 #define mmMMVM_PCIE_ATS_CNTL_VF_19 0x081b 1687 #define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 0 1688 #define mmMMVM_PCIE_ATS_CNTL_VF_20 0x081c 1689 #define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 0 1690 #define mmMMVM_PCIE_ATS_CNTL_VF_21 0x081d 1691 #define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 0 1692 #define mmMMVM_PCIE_ATS_CNTL_VF_22 0x081e 1693 #define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 0 1694 #define mmMMVM_PCIE_ATS_CNTL_VF_23 0x081f 1695 #define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 0 1696 #define mmMMVM_PCIE_ATS_CNTL_VF_24 0x0820 1697 #define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 0 1698 #define mmMMVM_PCIE_ATS_CNTL_VF_25 0x0821 1699 #define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 0 1700 #define mmMMVM_PCIE_ATS_CNTL_VF_26 0x0822 1701 #define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 0 1702 #define mmMMVM_PCIE_ATS_CNTL_VF_27 0x0823 1703 #define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 0 1704 #define mmMMVM_PCIE_ATS_CNTL_VF_28 0x0824 1705 #define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 0 1706 #define mmMMVM_PCIE_ATS_CNTL_VF_29 0x0825 1707 #define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 0 1708 #define mmMMVM_PCIE_ATS_CNTL_VF_30 0x0826 1709 #define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 0 1710 #define mmMMVM_PCIE_ATS_CNTL_VF_31 0x0827 1711 #define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 0 1712 #define mmMMUTCL2_CGTT_CLK_CTRL 0x0828 1713 #define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 1714 #define mmMMMC_SHARED_ACTIVE_FCN_ID 0x0829 1715 #define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 1716 1717 1718 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1719 // base address: 0x6a140 1720 #define mmMMMC_VM_NB_MMIOBASE 0x0850 1721 #define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 0 1722 #define mmMMMC_VM_NB_MMIOLIMIT 0x0851 1723 #define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1724 #define mmMMMC_VM_NB_PCI_CTRL 0x0852 1725 #define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 0 1726 #define mmMMMC_VM_NB_PCI_ARB 0x0853 1727 #define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 0 1728 #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0854 1729 #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1730 #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0855 1731 #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1732 #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0856 1733 #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1734 #define mmMMMC_VM_FB_OFFSET 0x0857 1735 #define mmMMMC_VM_FB_OFFSET_BASE_IDX 0 1736 #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0858 1737 #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1738 #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0859 1739 #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1740 #define mmMMMC_VM_STEERING 0x085a 1741 #define mmMMMC_VM_STEERING_BASE_IDX 0 1742 #define mmMMMC_SHARED_VIRT_RESET_REQ 0x085b 1743 #define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1744 #define mmMMMC_MEM_POWER_LS 0x085c 1745 #define mmMMMC_MEM_POWER_LS_BASE_IDX 0 1746 #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x085d 1747 #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1748 #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x085e 1749 #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1750 #define mmMMMC_VM_APT_CNTL 0x085f 1751 #define mmMMMC_VM_APT_CNTL_BASE_IDX 0 1752 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0860 1753 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1754 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x0861 1755 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1756 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x0862 1757 #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1758 #define mmMMMC_SHARED_VIRT_RESET_REQ2 0x0863 1759 #define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0 1760 1761 1762 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1763 // base address: 0x6a1b0 1764 #define mmMMMC_VM_FB_LOCATION_BASE 0x086c 1765 #define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1766 #define mmMMMC_VM_FB_LOCATION_TOP 0x086d 1767 #define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1768 #define mmMMMC_VM_AGP_TOP 0x086e 1769 #define mmMMMC_VM_AGP_TOP_BASE_IDX 0 1770 #define mmMMMC_VM_AGP_BOT 0x086f 1771 #define mmMMMC_VM_AGP_BOT_BASE_IDX 0 1772 #define mmMMMC_VM_AGP_BASE 0x0870 1773 #define mmMMMC_VM_AGP_BASE_BASE_IDX 0 1774 #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0871 1775 #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1776 #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0872 1777 #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1778 #define mmMMMC_VM_MX_L1_TLB_CNTL 0x0873 1779 #define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1780 1781 1782 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1783 // base address: 0x6a200 1784 #define mmMM_ATC_L2_PERFCOUNTER_LO 0x0880 1785 #define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0 1786 #define mmMM_ATC_L2_PERFCOUNTER_HI 0x0881 1787 #define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0 1788 1789 1790 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1791 // base address: 0x6a220 1792 #define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0888 1793 #define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1794 #define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0889 1795 #define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1796 #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x088a 1797 #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1798 1799 #endif 1800