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Searched refs:mmCP_RB1_WPTR (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2128 return RREG32(mmCP_RB1_WPTR); in gfx_v6_0_ring_get_wptr()
2148 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_compute()
2149 (void)RREG32(mmCP_RB1_WPTR); in gfx_v6_0_ring_set_wptr_compute()
2180 WREG32(mmCP_RB1_WPTR, ring->wptr); in gfx_v6_0_cp_compute_resume()
Dgfx_v10_0.c6218 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h505 #define mmCP_RB1_WPTR 0x3064 macro
Dgfx_7_0_d.h216 #define mmCP_RB1_WPTR 0x3064 macro
Dgfx_7_2_d.h216 #define mmCP_RB1_WPTR 0x3064 macro
Dgfx_8_0_d.h240 #define mmCP_RB1_WPTR 0x3064 macro
Dgfx_8_1_d.h241 #define mmCP_RB1_WPTR 0x3064 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2428 #define mmCP_RB1_WPTR macro
Dgc_9_1_offset.h2705 #define mmCP_RB1_WPTR macro
Dgc_9_2_1_offset.h2643 #define mmCP_RB1_WPTR macro
Dgc_10_1_0_offset.h4769 #define mmCP_RB1_WPTR macro
Dgc_10_3_0_offset.h4420 #define mmCP_RB1_WPTR macro