Searched refs:mmCP_MEC_CNTL (Results 1 – 17 of 17) sorted by relevance
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/inc/ |
D | polaris10_pwrvirus.h | 52 { 0x50000000, mmCP_MEC_CNTL }, 1502 { 0x00000000, mmCP_MEC_CNTL }, 1503 { 0x00000000, mmCP_MEC_CNTL },
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/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | smu8_smumgr.c | 192 mmCP_MEC_CNTL); in smu8_load_mec_firmware() 195 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); in smu8_load_mec_firmware()
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D | fiji_smumgr.c | 213 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in fiji_start_avfs_btc()
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D | polaris10_smumgr.c | 111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
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/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/ |
D | gfx_7_0_d.h | 319 #define mmCP_MEC_CNTL 0x208d macro
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D | gfx_7_2_d.h | 322 #define mmCP_MEC_CNTL 0x208d macro
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D | gfx_8_0_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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D | gfx_8_1_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v7_0.c | 2667 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable() 2669 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | in gfx_v7_0_cp_compute_enable() 4658 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
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D | gfx_v9_0.c | 3189 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable() 3191 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
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D | gfx_v8_0.c | 4319 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable() 4321 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
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D | gfx_v10_0.c | 6273 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v10_0_cp_compute_enable() 6291 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
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/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/ |
D | gc_9_0_offset.h | 135 #define mmCP_MEC_CNTL … macro
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D | gc_9_1_offset.h | 135 #define mmCP_MEC_CNTL … macro
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D | gc_9_2_1_offset.h | 137 #define mmCP_MEC_CNTL … macro
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D | gc_10_1_0_offset.h | 2143 #define mmCP_MEC_CNTL … macro
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D | gc_10_3_0_offset.h | 2278 #define mmCP_MEC_CNTL … macro
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