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Searched refs:mmCP_ME1_PIPE0_INT_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h265 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
Dgfx_7_2_d.h267 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
Dgfx_8_0_d.h298 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
Dgfx_8_1_d.h298 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2501 #define mmCP_ME1_PIPE0_INT_CNTL … macro
Dgc_9_1_offset.h2775 #define mmCP_ME1_PIPE0_INT_CNTL … macro
Dgc_9_2_1_offset.h2711 #define mmCP_ME1_PIPE0_INT_CNTL … macro
Dgc_10_1_0_offset.h4839 #define mmCP_ME1_PIPE0_INT_CNTL … macro
Dgc_10_3_0_offset.h4498 #define mmCP_ME1_PIPE0_INT_CNTL … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c4729 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c9004 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9238 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
Dgfx_v9_0.c5544 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6457 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()