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Searched refs:mmCP_CE_IC_BASE_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h10255 #define mmCP_CE_IC_BASE_CNTL … macro
Dgc_10_3_0_offset.h9981 #define mmCP_CE_IC_BASE_CNTL … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c5885 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()