1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28 
29 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
30 #include "dcn20/dcn20_clk_mgr.h"
31 #include "dce100/dce_clk_mgr.h"
32 #include "dcn31/dcn31_clk_mgr.h"
33 #include "reg_helper.h"
34 #include "core_types.h"
35 #include "dm_helpers.h"
36 #include "dc_link_dp.h"
37 
38 #include "atomfirmware.h"
39 #include "smu13_driver_if.h"
40 
41 #include "dcn/dcn_3_2_0_offset.h"
42 #include "dcn/dcn_3_2_0_sh_mask.h"
43 
44 #include "dcn32/dcn32_clk_mgr.h"
45 #include "dml/dcn32/dcn32_fpu.h"
46 
47 #define DCN_BASE__INST0_SEG1                       0x000000C0
48 
49 #define mmCLK1_CLK_PLL_REQ                              0x16E37
50 #define mmCLK1_CLK0_DFS_CNTL                            0x16E69
51 #define mmCLK1_CLK1_DFS_CNTL                            0x16E6C
52 #define mmCLK1_CLK2_DFS_CNTL                            0x16E6F
53 #define mmCLK1_CLK3_DFS_CNTL                            0x16E72
54 #define mmCLK1_CLK4_DFS_CNTL                            0x16E75
55 
56 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffUL
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000UL
58 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000UL
59 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
61 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
62 
63 #define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E37
64 #define mmCLK01_CLK0_CLK0_DFS_CNTL                      0x16E64
65 #define mmCLK01_CLK0_CLK1_DFS_CNTL                      0x16E67
66 #define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E6A
67 #define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E6D
68 #define mmCLK01_CLK0_CLK4_DFS_CNTL                      0x16E70
69 
70 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffL
71 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000L
72 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000L
73 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
74 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
75 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
76 
77 #undef FN
78 #define FN(reg_name, field_name) \
79 	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
80 
81 #define REG(reg) \
82 	(clk_mgr->regs->reg)
83 
84 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
85 
86 #define BASE(seg) BASE_INNER(seg)
87 
88 #define SR(reg_name)\
89 		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
90 					reg ## reg_name
91 
92 #define CLK_SR_DCN32(reg_name)\
93 	.reg_name = mm ## reg_name
94 
95 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
96 	CLK_REG_LIST_DCN32()
97 };
98 
99 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
100 	CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
101 };
102 
103 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
104 	CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
105 };
106 
107 
108 #define CLK_SR_DCN321(reg_name, block, inst)\
109 	.reg_name = mm ## block ## _ ## reg_name
110 
111 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
112 	CLK_REG_LIST_DCN321()
113 };
114 
115 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
116 	CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
117 };
118 
119 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
120 	CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
121 };
122 
123 
124 /* Query SMU for all clock states for a particular clock */
dcn32_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)125 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
126 		unsigned int *num_levels)
127 {
128 	unsigned int i;
129 	char *entry_i = (char *)entry_0;
130 
131 	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
132 
133 	if (ret & (1 << 31))
134 		/* fine-grained, only min and max */
135 		*num_levels = 2;
136 	else
137 		/* discrete, a number of fixed states */
138 		/* will set num_levels to 0 on failure */
139 		*num_levels = ret & 0xFF;
140 
141 	/* if the initial message failed, num_levels will be 0 */
142 	for (i = 0; i < *num_levels; i++) {
143 		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
144 		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
145 	}
146 }
147 
dcn32_build_wm_range_table(struct clk_mgr_internal * clk_mgr)148 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
149 {
150 	DC_FP_START();
151 	dcn32_build_wm_range_table_fpu(clk_mgr);
152 	DC_FP_END();
153 }
154 
dcn32_init_clocks(struct clk_mgr * clk_mgr_base)155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
156 {
157 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
158 	unsigned int num_levels;
159 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
160 	unsigned int i;
161 
162 	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
163 	clk_mgr_base->clks.p_state_change_support = true;
164 	clk_mgr_base->clks.prev_p_state_change_support = true;
165 	clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
166 	clk_mgr->smu_present = false;
167 	clk_mgr->dpm_present = false;
168 
169 	if (!clk_mgr_base->bw_params)
170 		return;
171 
172 	if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
173 		clk_mgr->smu_present = true;
174 
175 	if (!clk_mgr->smu_present)
176 		return;
177 
178 	dcn30_smu_check_driver_if_version(clk_mgr);
179 	dcn30_smu_check_msg_header_version(clk_mgr);
180 
181 	/* DCFCLK */
182 	dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
183 			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
184 			&num_entries_per_clk->num_dcfclk_levels);
185 
186 	/* SOCCLK */
187 	dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
188 					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
189 					&num_entries_per_clk->num_socclk_levels);
190 
191 	/* DTBCLK */
192 	if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
193 		dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
194 				&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
195 				&num_entries_per_clk->num_dtbclk_levels);
196 
197 	/* DISPCLK */
198 	dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
199 			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
200 			&num_entries_per_clk->num_dispclk_levels);
201 	num_levels = num_entries_per_clk->num_dispclk_levels;
202 
203 	if (num_entries_per_clk->num_dcfclk_levels &&
204 			num_entries_per_clk->num_dtbclk_levels &&
205 			num_entries_per_clk->num_dispclk_levels)
206 		clk_mgr->dpm_present = true;
207 
208 	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
209 		for (i = 0; i < num_levels; i++)
210 			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
211 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
212 				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
213 					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
214 	}
215 	for (i = 0; i < num_levels; i++)
216 		if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
217 			clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
218 
219 	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
220 		for (i = 0; i < num_levels; i++)
221 			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
222 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
223 				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
224 					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
225 	}
226 
227 	/* Get UCLK, update bounding box */
228 	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
229 
230 	DC_FP_START();
231 	/* WM range table */
232 	dcn32_build_wm_range_table(clk_mgr);
233 	DC_FP_END();
234 }
235 
dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)236 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
237 			struct dc_state *context,
238 			int ref_dtbclk_khz)
239 {
240 	struct dccg *dccg = clk_mgr->dccg;
241 	uint32_t tg_mask = 0;
242 	int i;
243 
244 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
245 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
246 		struct dtbclk_dto_params dto_params = {0};
247 
248 		/* use mask to program DTO once per tg */
249 		if (pipe_ctx->stream_res.tg &&
250 				!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
251 			tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
252 
253 			dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
254 			dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
255 
256 			if (is_dp_128b_132b_signal(pipe_ctx)) {
257 				dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk;
258 
259 				if (pipe_ctx->stream_res.audio != NULL)
260 					dto_params.req_audio_dtbclk_khz = 24000;
261 			}
262 			if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
263 				dto_params.is_hdmi = true;
264 
265 			dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
266 			//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
267 		}
268 	}
269 }
270 
271 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
272  * update DPPCLK to be the exact frequency that will be set after the DPPCLK
273  * divider is updated. This will prevent rounding issues that could cause DPP
274  * refclk and DPP DTO to not match up.
275  */
dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)276 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
277 {
278 	int dpp_divider = 0;
279 	int disp_divider = 0;
280 
281 	if (new_clocks->dppclk_khz) {
282 		dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
283 				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
284 		new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
285 	}
286 	if (new_clocks->dispclk_khz > 0) {
287 		disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
288 				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
289 		new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
290 	}
291 }
292 
dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)293 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
294 			struct dc_state *context,
295 			bool safe_to_lower)
296 {
297 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
298 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
299 	struct dc *dc = clk_mgr_base->ctx->dc;
300 	int display_count;
301 	bool update_dppclk = false;
302 	bool update_dispclk = false;
303 	bool enter_display_off = false;
304 	bool dpp_clock_lowered = false;
305 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
306 	bool force_reset = false;
307 	bool update_uclk = false, update_fclk = false;
308 	bool p_state_change_support;
309 	bool fclk_p_state_change_support;
310 	int total_plane_count;
311 
312 	if (dc->work_arounds.skip_clock_update)
313 		return;
314 
315 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
316 			(dc->debug.force_clock_mode & 0x1)) {
317 		/* This is from resume or boot up, if forced_clock cfg option used,
318 		 * we bypass program dispclk and DPPCLK, but need set them for S3.
319 		 */
320 		force_reset = true;
321 
322 		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
323 
324 		/* Force_clock_mode 0x1:  force reset the clock even it is the same clock
325 		 * as long as it is in Passive level.
326 		 */
327 	}
328 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
329 
330 	if (display_count == 0)
331 		enter_display_off = true;
332 
333 	if (clk_mgr->smu_present) {
334 		if (enter_display_off == safe_to_lower)
335 			dcn30_smu_set_num_of_displays(clk_mgr, display_count);
336 
337 		clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
338 
339 		total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
340 		fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
341 
342 		if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
343 			clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
344 
345 			/* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
346 			if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
347 				/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
348 				dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
349 			}
350 		}
351 
352 		if (dc->debug.force_min_dcfclk_mhz > 0)
353 			new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
354 					new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
355 
356 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
357 			clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
358 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
359 		}
360 
361 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
362 			clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
363 			dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
364 		}
365 
366 		if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
367 			/* We don't actually care about socclk, don't notify SMU of hard min */
368 			clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
369 
370 		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
371 		clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
372 
373 		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
374 				clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
375 			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
376 			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
377 		}
378 
379 
380 		p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
381 		if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
382 			clk_mgr_base->clks.p_state_change_support = p_state_change_support;
383 
384 			/* to disable P-State switching, set UCLK min = max */
385 			if (!clk_mgr_base->clks.p_state_change_support)
386 				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
387 						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
388 		}
389 
390 		/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
391 		if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
392 			update_fclk = true;
393 		}
394 
395 		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
396 			/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
397 			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
398 		}
399 
400 		/* Always update saved value, even if new value not set due to P-State switching unsupported */
401 		if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
402 			clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
403 			update_uclk = true;
404 		}
405 
406 		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
407 		if (clk_mgr_base->clks.p_state_change_support &&
408 				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
409 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
410 
411 		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
412 				clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
413 			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
414 			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
415 		}
416 	}
417 
418 	dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
419 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
420 		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
421 			dpp_clock_lowered = true;
422 
423 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
424 
425 		if (clk_mgr->smu_present && !dpp_clock_lowered)
426 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
427 
428 		update_dppclk = true;
429 	}
430 
431 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
432 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
433 
434 		if (clk_mgr->smu_present)
435 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
436 
437 		update_dispclk = true;
438 	}
439 
440 	if (!new_clocks->dtbclk_en) {
441 		new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
442 	}
443 
444 	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
445 	if (!dc->debug.disable_dtb_ref_clk_switch &&
446 			should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
447 		/* DCCG requires KHz precision for DTBCLK */
448 		clk_mgr_base->clks.ref_dtbclk_khz =
449 				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
450 
451 		dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
452 	}
453 
454 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
455 		if (dpp_clock_lowered) {
456 			/* if clock is being lowered, increase DTO before lowering refclk */
457 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
458 			dcn20_update_clocks_update_dentist(clk_mgr, context);
459 			if (clk_mgr->smu_present)
460 				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
461 		} else {
462 			/* if clock is being raised, increase refclk before lowering DTO */
463 			if (update_dppclk || update_dispclk)
464 				dcn20_update_clocks_update_dentist(clk_mgr, context);
465 			/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
466 			 * that we do not lower dto when it is not safe to lower. We do not need to
467 			 * compare the current and new dppclk before calling this function.
468 			 */
469 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
470 		}
471 	}
472 
473 	if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
474 		/*update dmcu for wait_loop count*/
475 		dmcu->funcs->set_psr_wait_loop(dmcu,
476 				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
477 }
478 
dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)479 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
480 {
481 		struct fixed31_32 pll_req;
482 		uint32_t pll_req_reg = 0;
483 
484 		/* get FbMult value */
485 		if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
486 			pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
487 		else
488 			pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
489 
490 		/* set up a fixed-point number
491 		 * this works because the int part is on the right edge of the register
492 		 * and the frac part is on the left edge
493 		 */
494 		pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
495 		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
496 
497 		/* multiply by REFCLK period */
498 		pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
499 
500 		return dc_fixpt_floor(pll_req);
501 }
502 
dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)503 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
504 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
505 {
506 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
507 	uint32_t dprefclk_did = 0;
508 	uint32_t dcfclk_did = 0;
509 	uint32_t dtbclk_did = 0;
510 	uint32_t dispclk_did = 0;
511 	uint32_t dppclk_did = 0;
512 	uint32_t target_div = 0;
513 
514 	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
515 		/* DFS Slice 0 is used for DISPCLK */
516 		dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
517 		/* DFS Slice 1 is used for DPPCLK */
518 		dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
519 		/* DFS Slice 2 is used for DPREFCLK */
520 		dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
521 		/* DFS Slice 3 is used for DCFCLK */
522 		dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
523 		/* DFS Slice 4 is used for DTBCLK */
524 		dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
525 	} else {
526 		/* DFS Slice 0 is used for DISPCLK */
527 		dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
528 		/* DFS Slice 1 is used for DPPCLK */
529 		dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
530 		/* DFS Slice 2 is used for DPREFCLK */
531 		dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
532 		/* DFS Slice 3 is used for DCFCLK */
533 		dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
534 		/* DFS Slice 4 is used for DTBCLK */
535 		dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
536 	}
537 
538 	/* Convert DISPCLK DFS Slice DID to divider*/
539 	target_div = dentist_get_divider_from_did(dispclk_did);
540 	//Get dispclk in khz
541 	regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
542 			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
543 
544 	/* Convert DISPCLK DFS Slice DID to divider*/
545 	target_div = dentist_get_divider_from_did(dppclk_did);
546 	//Get dppclk in khz
547 	regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
548 			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
549 
550 	/* Convert DPREFCLK DFS Slice DID to divider*/
551 	target_div = dentist_get_divider_from_did(dprefclk_did);
552 	//Get dprefclk in khz
553 	regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
554 			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
555 
556 	/* Convert DCFCLK DFS Slice DID to divider*/
557 	target_div = dentist_get_divider_from_did(dcfclk_did);
558 	//Get dcfclk in khz
559 	regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
560 			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
561 
562 	/* Convert DTBCLK DFS Slice DID to divider*/
563 	target_div = dentist_get_divider_from_did(dtbclk_did);
564 	//Get dtbclk in khz
565 	regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
566 			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
567 }
568 
dcn32_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)569 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
570 {
571 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
572 	int ss_info_num = bp->funcs->get_ss_entry_number(
573 			bp, AS_SIGNAL_TYPE_GPU_PLL);
574 
575 	if (ss_info_num) {
576 		struct spread_spectrum_info info = { { 0 } };
577 		enum bp_result result = bp->funcs->get_spread_spectrum_info(
578 				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
579 
580 		/* SSInfo.spreadSpectrumPercentage !=0 would be sign
581 		 * that SS is enabled
582 		 */
583 		if (result == BP_RESULT_OK &&
584 				info.spread_spectrum_percentage != 0) {
585 			clk_mgr->ss_on_dprefclk = true;
586 			clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
587 
588 			if (info.type.CENTER_MODE == 0) {
589 				/* Currently for DP Reference clock we
590 				 * need only SS percentage for
591 				 * downspread
592 				 */
593 				clk_mgr->dprefclk_ss_percentage =
594 						info.spread_spectrum_percentage;
595 			}
596 		}
597 	}
598 }
dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base)599 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
600 {
601 	unsigned int i;
602 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
603 	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
604 
605 	if (!clk_mgr->smu_present)
606 		return;
607 
608 	if (!table)
609 		return;
610 
611 	memset(table, 0, sizeof(*table));
612 
613 	/* collect valid ranges, place in pmfw table */
614 	for (i = 0; i < WM_SET_COUNT; i++)
615 		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
616 			table->Watermarks.WatermarkRow[i].WmSetting = i;
617 			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
618 		}
619 	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
620 	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
621 	dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
622 }
623 
624 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)625 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
626 {
627 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
628 
629 	if (!clk_mgr->smu_present)
630 		return;
631 
632 	if (current_mode) {
633 		if (clk_mgr_base->clks.p_state_change_support)
634 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
635 					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
636 		else
637 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
638 					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
639 	} else {
640 		dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
641 				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
642 	}
643 }
644 
645 /* Set max memclk to highest DPM value */
dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)646 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
647 {
648 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
649 
650 	if (!clk_mgr->smu_present)
651 		return;
652 
653 	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
654 			clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
655 }
656 
657 /* Get current memclk states, update bounding box */
dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)658 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
659 {
660 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
661 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
662 	unsigned int num_levels;
663 
664 	if (!clk_mgr->smu_present)
665 		return;
666 
667 	/* Refresh memclk and fclk states */
668 	dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
669 			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
670 			&num_entries_per_clk->num_memclk_levels);
671 
672 	/* memclk must have at least one level */
673 	num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
674 
675 	dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
676 			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
677 			&num_entries_per_clk->num_fclk_levels);
678 
679 	if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
680 		num_levels = num_entries_per_clk->num_memclk_levels;
681 	} else {
682 		num_levels = num_entries_per_clk->num_fclk_levels;
683 	}
684 
685 	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
686 
687 	if (clk_mgr->dpm_present && !num_levels)
688 		clk_mgr->dpm_present = false;
689 
690 	if (!clk_mgr->dpm_present)
691 		dcn32_patch_dpm_table(clk_mgr_base->bw_params);
692 
693 	DC_FP_START();
694 	/* Refresh bounding box */
695 	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
696 			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
697 	DC_FP_END();
698 }
699 
dcn32_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)700 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
701 					struct dc_clocks *b)
702 {
703 	if (a->dispclk_khz != b->dispclk_khz)
704 		return false;
705 	else if (a->dppclk_khz != b->dppclk_khz)
706 		return false;
707 	else if (a->dcfclk_khz != b->dcfclk_khz)
708 		return false;
709 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
710 		return false;
711 	else if (a->dramclk_khz != b->dramclk_khz)
712 		return false;
713 	else if (a->p_state_change_support != b->p_state_change_support)
714 		return false;
715 	else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
716 		return false;
717 
718 	return true;
719 }
720 
dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base)721 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
722 {
723 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
724 
725 	if (!clk_mgr->smu_present)
726 		return;
727 
728 	dcn32_smu_set_pme_workaround(clk_mgr);
729 }
730 
dcn32_is_smu_present(struct clk_mgr * clk_mgr_base)731 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
732 {
733 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
734 	return clk_mgr->smu_present;
735 }
736 
737 
738 static struct clk_mgr_funcs dcn32_funcs = {
739 		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
740 		.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
741 		.update_clocks = dcn32_update_clocks,
742 		.dump_clk_registers = dcn32_dump_clk_registers,
743 		.init_clocks = dcn32_init_clocks,
744 		.notify_wm_ranges = dcn32_notify_wm_ranges,
745 		.set_hard_min_memclk = dcn32_set_hard_min_memclk,
746 		.set_hard_max_memclk = dcn32_set_hard_max_memclk,
747 		.get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
748 		.are_clock_states_equal = dcn32_are_clock_states_equal,
749 		.enable_pme_wa = dcn32_enable_pme_wa,
750 		.is_smu_present = dcn32_is_smu_present,
751 };
752 
dcn32_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)753 void dcn32_clk_mgr_construct(
754 		struct dc_context *ctx,
755 		struct clk_mgr_internal *clk_mgr,
756 		struct pp_smu_funcs *pp_smu,
757 		struct dccg *dccg)
758 {
759 	clk_mgr->base.ctx = ctx;
760 	clk_mgr->base.funcs = &dcn32_funcs;
761 	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
762 		clk_mgr->regs = &clk_mgr_regs_dcn321;
763 		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
764 		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
765 	} else {
766 		clk_mgr->regs = &clk_mgr_regs_dcn32;
767 		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
768 		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
769 	}
770 
771 	clk_mgr->dccg = dccg;
772 	clk_mgr->dfs_bypass_disp_clk = 0;
773 
774 	clk_mgr->dprefclk_ss_percentage = 0;
775 	clk_mgr->dprefclk_ss_divider = 1000;
776 	clk_mgr->ss_on_dprefclk = false;
777 	clk_mgr->dfs_ref_freq_khz = 100000;
778 
779 	/* Changed from DCN3.2_clock_frequency doc to match
780 	 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
781 	 * dprefclk DID divider
782 	 */
783 	clk_mgr->base.dprefclk_khz = 716666;
784 	if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
785 		//initialize DTB ref clock value if DPM disabled
786 		if (ctx->dce_version == DCN_VERSION_3_21)
787 			clk_mgr->base.clks.ref_dtbclk_khz = 477800;
788 		else
789 			clk_mgr->base.clks.ref_dtbclk_khz = 268750;
790 	}
791 
792 	/* integer part is now VCO frequency in kHz */
793 	clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
794 
795 	/* in case we don't get a value from the register, use default */
796 	if (clk_mgr->base.dentist_vco_freq_khz == 0)
797 		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
798 
799 	if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
800 			clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
801 		clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
802 	}
803 
804 	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
805 		clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
806 	}
807 	dcn32_clock_read_ss_info(clk_mgr);
808 
809 	clk_mgr->dfs_bypass_enabled = false;
810 
811 	clk_mgr->smu_present = false;
812 
813 	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
814 
815 	/* need physical address of table to give to PMFW */
816 	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
817 			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
818 			&clk_mgr->wm_range_table_addr);
819 }
820 
dcn32_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)821 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
822 {
823 	if (clk_mgr->base.bw_params)
824 		kfree(clk_mgr->base.bw_params);
825 
826 	if (clk_mgr->wm_range_table)
827 		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
828 				clk_mgr->wm_range_table);
829 }
830 
831