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Searched refs:mmCGTS_SA0_QUAD1_SM_CTRL_REG (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h9881 #define mmCGTS_SA0_QUAD1_SM_CTRL_REG macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c8011 mmCGTS_SA0_QUAD1_SM_CTRL_REG, in gfx_v10_0_apply_medium_grain_clock_gating_workaround()