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Searched refs:mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h7144 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
Ddcn_2_0_0_offset.h8175 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1311 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro