Searched refs:mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 (Results 1 – 2 of 2) sorted by relevance
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
2606 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 … macro