1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/ethtool.h>
40 #include <linux/list.h>
41 #include <linux/mutex.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/net_tstamp.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
47 #endif
48 #include <linux/cpu_rmap.h>
49 #include <linux/ptp_clock_kernel.h>
50 #include <linux/irq.h>
51 #include <net/xdp.h>
52
53 #include <linux/mlx4/device.h>
54 #include <linux/mlx4/qp.h>
55 #include <linux/mlx4/cq.h>
56 #include <linux/mlx4/srq.h>
57 #include <linux/mlx4/doorbell.h>
58 #include <linux/mlx4/cmd.h>
59
60 #include "en_port.h"
61 #include "mlx4_stats.h"
62
63 #define DRV_NAME "mlx4_en"
64 #define DRV_VERSION "4.0-0"
65
66 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
67
68 /*
69 * Device constants
70 */
71
72
73 #define MLX4_EN_PAGE_SHIFT 12
74 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
75 #define DEF_RX_RINGS 16
76 #define MAX_RX_RINGS 128
77 #define MIN_RX_RINGS 1
78 #define LOG_TXBB_SIZE 6
79 #define TXBB_SIZE BIT(LOG_TXBB_SIZE)
80 #define HEADROOM (2048 / TXBB_SIZE + 1)
81 #define STAMP_STRIDE 64
82 #define STAMP_DWORDS (STAMP_STRIDE / 4)
83 #define STAMP_SHIFT 31
84 #define STAMP_VAL 0x7fffffff
85 #define STATS_DELAY (HZ / 4)
86 #define SERVICE_TASK_DELAY (HZ / 4)
87 #define MAX_NUM_OF_FS_RULES 256
88
89 #define MLX4_EN_FILTER_HASH_SHIFT 4
90 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
91
92 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
93 #define MAX_DESC_SIZE 512
94 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
95
96 /*
97 * OS related constants and tunables
98 */
99
100 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
101 #define MLX4_EN_PRIV_FLAGS_PHV 2
102
103 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
104
105 /* Use the maximum between 16384 and a single page */
106 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
107
108 #define MLX4_EN_MAX_RX_FRAGS 4
109
110 /* Maximum ring sizes */
111 #define MLX4_EN_MAX_TX_SIZE 8192
112 #define MLX4_EN_MAX_RX_SIZE 8192
113
114 /* Minimum ring size for our page-allocation scheme to work */
115 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
116 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
117
118 #define MLX4_EN_SMALL_PKT_SIZE 64
119 #define MLX4_EN_MIN_TX_RING_P_UP 1
120 #define MLX4_EN_MAX_TX_RING_P_UP 32
121 #define MLX4_EN_NUM_UP_LOW 1
122 #define MLX4_EN_NUM_UP_HIGH 8
123 #define MLX4_EN_DEF_RX_RING_SIZE 1024
124 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
125 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
126 MLX4_EN_NUM_UP_HIGH)
127
128 #define MLX4_EN_DEFAULT_TX_WORK 256
129
130 /* Target number of packets to coalesce with interrupt moderation */
131 #define MLX4_EN_RX_COAL_TARGET 44
132 #define MLX4_EN_RX_COAL_TIME 0x10
133
134 #define MLX4_EN_TX_COAL_PKTS 16
135 #define MLX4_EN_TX_COAL_TIME 0x10
136
137 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
138 #define MLX4_EN_MAX_COAL_TIME U16_MAX
139
140 #define MLX4_EN_RX_RATE_LOW 400000
141 #define MLX4_EN_RX_COAL_TIME_LOW 0
142 #define MLX4_EN_RX_RATE_HIGH 450000
143 #define MLX4_EN_RX_COAL_TIME_HIGH 128
144 #define MLX4_EN_RX_SIZE_THRESH 1024
145 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
146 #define MLX4_EN_SAMPLE_INTERVAL 0
147 #define MLX4_EN_AVG_PKT_SMALL 256
148
149 #define MLX4_EN_AUTO_CONF 0xffff
150
151 #define MLX4_EN_DEF_RX_PAUSE 1
152 #define MLX4_EN_DEF_TX_PAUSE 1
153
154 /* Interval between successive polls in the Tx routine when polling is used
155 instead of interrupts (in per-core Tx rings) - should be power of 2 */
156 #define MLX4_EN_TX_POLL_MODER 16
157 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
158
159 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
160 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
161 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
162 #define PREAMBLE_LEN 8
163 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
164 ETH_HLEN + PREAMBLE_LEN)
165
166 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
167 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
168 */
169 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
170 #define ETH_BCAST 0xffffffffffffULL
171
172 #define MLX4_EN_LOOPBACK_RETRIES 5
173 #define MLX4_EN_LOOPBACK_TIMEOUT 100
174
175 /* Constants for TX flow */
176 enum {
177 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
178 MAX_BF = 256,
179 MIN_PKT_LEN = 17,
180 };
181
182 /*
183 * Configurables
184 */
185
186 enum cq_type {
187 /* keep tx types first */
188 TX,
189 TX_XDP,
190 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
191 RX,
192 };
193
194
195 /*
196 * Useful macros
197 */
198 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
199 #define XNOR(x, y) (!(x) == !(y))
200
201
202 struct mlx4_en_tx_info {
203 union {
204 struct sk_buff *skb;
205 struct page *page;
206 };
207 dma_addr_t map0_dma;
208 u32 map0_byte_count;
209 u32 nr_txbb;
210 u32 nr_bytes;
211 u8 linear;
212 u8 data_offset;
213 u8 inl;
214 u8 ts_requested;
215 u8 nr_maps;
216 } ____cacheline_aligned_in_smp;
217
218
219 #define MLX4_EN_BIT_DESC_OWN 0x80000000
220 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
221 #define MLX4_EN_MEMTYPE_PAD 0x100
222 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
223
224
225 struct mlx4_en_tx_desc {
226 struct mlx4_wqe_ctrl_seg ctrl;
227 union {
228 struct mlx4_wqe_data_seg data; /* at least one data segment */
229 struct mlx4_wqe_lso_seg lso;
230 struct mlx4_wqe_inline_seg inl;
231 };
232 };
233
234 #define MLX4_EN_USE_SRQ 0x01000000
235
236 #define MLX4_EN_CX3_LOW_ID 0x1000
237 #define MLX4_EN_CX3_HIGH_ID 0x1005
238
239 struct mlx4_en_rx_alloc {
240 struct page *page;
241 dma_addr_t dma;
242 u32 page_offset;
243 };
244
245 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
246
247 struct mlx4_en_page_cache {
248 u32 index;
249 struct {
250 struct page *page;
251 dma_addr_t dma;
252 } buf[MLX4_EN_CACHE_SIZE];
253 };
254
255 enum {
256 MLX4_EN_TX_RING_STATE_RECOVERING,
257 };
258
259 struct mlx4_en_priv;
260
261 struct mlx4_en_tx_ring {
262 /* cache line used and dirtied in tx completion
263 * (mlx4_en_free_tx_buf())
264 */
265 u32 last_nr_txbb;
266 u32 cons;
267 unsigned long wake_queue;
268 struct netdev_queue *tx_queue;
269 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
270 struct mlx4_en_tx_ring *ring,
271 int index,
272 u64 timestamp, int napi_mode);
273 struct mlx4_en_rx_ring *recycle_ring;
274
275 /* cache line used and dirtied in mlx4_en_xmit() */
276 u32 prod ____cacheline_aligned_in_smp;
277 unsigned int tx_dropped;
278 unsigned long bytes;
279 unsigned long packets;
280 unsigned long tx_csum;
281 unsigned long tso_packets;
282 unsigned long xmit_more;
283 struct mlx4_bf bf;
284
285 /* Following part should be mostly read */
286 void __iomem *doorbell_address;
287 __be32 doorbell_qpn;
288 __be32 mr_key;
289 u32 size; /* number of TXBBs */
290 u32 size_mask;
291 u32 full_size;
292 u32 buf_size;
293 void *buf;
294 struct mlx4_en_tx_info *tx_info;
295 int qpn;
296 u8 queue_index;
297 bool bf_enabled;
298 bool bf_alloced;
299 u8 hwtstamp_tx_type;
300 u8 *bounce_buf;
301
302 /* Not used in fast path
303 * Only queue_stopped might be used if BQL is not properly working.
304 */
305 unsigned long queue_stopped;
306 unsigned long state;
307 struct mlx4_hwq_resources sp_wqres;
308 struct mlx4_qp sp_qp;
309 struct mlx4_qp_context sp_context;
310 cpumask_t sp_affinity_mask;
311 enum mlx4_qp_state sp_qp_state;
312 u16 sp_stride;
313 u16 sp_cqn; /* index of port CQ associated with this ring */
314 } ____cacheline_aligned_in_smp;
315
316 struct mlx4_en_rx_desc {
317 /* actual number of entries depends on rx ring stride */
318 struct mlx4_wqe_data_seg data[0];
319 };
320
321 struct mlx4_en_rx_ring {
322 struct mlx4_hwq_resources wqres;
323 u32 size ; /* number of Rx descs*/
324 u32 actual_size;
325 u32 size_mask;
326 u16 stride;
327 u16 log_stride;
328 u16 cqn; /* index of port CQ associated with this ring */
329 u32 prod;
330 u32 cons;
331 u32 buf_size;
332 u8 fcs_del;
333 void *buf;
334 void *rx_info;
335 struct bpf_prog __rcu *xdp_prog;
336 struct mlx4_en_page_cache page_cache;
337 unsigned long bytes;
338 unsigned long packets;
339 unsigned long csum_ok;
340 unsigned long csum_none;
341 unsigned long csum_complete;
342 unsigned long rx_alloc_pages;
343 unsigned long xdp_drop;
344 unsigned long xdp_redirect;
345 unsigned long xdp_redirect_fail;
346 unsigned long xdp_tx;
347 unsigned long xdp_tx_full;
348 unsigned long dropped;
349 int hwtstamp_rx_filter;
350 cpumask_var_t affinity_mask;
351 struct xdp_rxq_info xdp_rxq;
352 };
353
354 struct mlx4_en_cq {
355 struct mlx4_cq mcq;
356 struct mlx4_hwq_resources wqres;
357 int ring;
358 struct net_device *dev;
359 union {
360 struct napi_struct napi;
361 bool xdp_busy;
362 };
363 int size;
364 int buf_size;
365 int vector;
366 enum cq_type type;
367 u16 moder_time;
368 u16 moder_cnt;
369 struct mlx4_cqe *buf;
370 #define MLX4_EN_OPCODE_ERROR 0x1e
371
372 const struct cpumask *aff_mask;
373 };
374
375 struct mlx4_en_port_profile {
376 u32 flags;
377 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
378 u32 rx_ring_num;
379 u32 tx_ring_size;
380 u32 rx_ring_size;
381 u8 num_tx_rings_p_up;
382 u8 rx_pause;
383 u8 rx_ppp;
384 u8 tx_pause;
385 u8 tx_ppp;
386 u8 num_up;
387 int rss_rings;
388 int inline_thold;
389 struct hwtstamp_config hwtstamp_config;
390 };
391
392 struct mlx4_en_profile {
393 int udp_rss;
394 u8 rss_mask;
395 u32 active_ports;
396 u32 small_pkt_int;
397 u8 no_reset;
398 u8 max_num_tx_rings_p_up;
399 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
400 };
401
402 struct mlx4_en_dev {
403 struct mlx4_dev *dev;
404 struct pci_dev *pdev;
405 struct mutex state_lock;
406 struct net_device *pndev[MLX4_MAX_PORTS + 1];
407 struct net_device *upper[MLX4_MAX_PORTS + 1];
408 u32 port_cnt;
409 bool device_up;
410 struct mlx4_en_profile profile;
411 u32 LSO_support;
412 struct workqueue_struct *workqueue;
413 struct device *dma_device;
414 void __iomem *uar_map;
415 struct mlx4_uar priv_uar;
416 struct mlx4_mr mr;
417 u32 priv_pdn;
418 spinlock_t uar_lock;
419 u8 mac_removed[MLX4_MAX_PORTS + 1];
420 u32 nominal_c_mult;
421 struct cyclecounter cycles;
422 seqlock_t clock_lock;
423 struct timecounter clock;
424 unsigned long last_overflow_check;
425 struct ptp_clock *ptp_clock;
426 struct ptp_clock_info ptp_clock_info;
427 struct notifier_block nb;
428 };
429
430
431 struct mlx4_en_rss_map {
432 int base_qpn;
433 struct mlx4_qp qps[MAX_RX_RINGS];
434 enum mlx4_qp_state state[MAX_RX_RINGS];
435 struct mlx4_qp *indir_qp;
436 enum mlx4_qp_state indir_state;
437 };
438
439 enum mlx4_en_port_flag {
440 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
441 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
442 };
443
444 struct mlx4_en_port_state {
445 int link_state;
446 int link_speed;
447 int transceiver;
448 u32 flags;
449 };
450
451 enum mlx4_en_mclist_act {
452 MCLIST_NONE,
453 MCLIST_REM,
454 MCLIST_ADD,
455 };
456
457 struct mlx4_en_mc_list {
458 struct list_head list;
459 enum mlx4_en_mclist_act action;
460 u8 addr[ETH_ALEN];
461 u64 reg_id;
462 u64 tunnel_reg_id;
463 };
464
465 struct mlx4_en_frag_info {
466 u16 frag_size;
467 u32 frag_stride;
468 };
469
470 #ifdef CONFIG_MLX4_EN_DCB
471 /* Minimal TC BW - setting to 0 will block traffic */
472 #define MLX4_EN_BW_MIN 1
473 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
474
475 #define MLX4_EN_TC_VENDOR 0
476 #define MLX4_EN_TC_ETS 7
477
478 enum dcb_pfc_type {
479 pfc_disabled = 0,
480 pfc_enabled_full,
481 pfc_enabled_tx,
482 pfc_enabled_rx
483 };
484
485 struct mlx4_en_cee_config {
486 bool pfc_state;
487 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
488 };
489 #endif
490
491 struct ethtool_flow_id {
492 struct list_head list;
493 struct ethtool_rx_flow_spec flow_spec;
494 u64 id;
495 };
496
497 enum {
498 MLX4_EN_FLAG_PROMISC = (1 << 0),
499 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
500 /* whether we need to enable hardware loopback by putting dmac
501 * in Tx WQE
502 */
503 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
504 /* whether we need to drop packets that hardware loopback-ed */
505 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
506 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
507 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
508 #ifdef CONFIG_MLX4_EN_DCB
509 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
510 #endif
511 };
512
513 #define PORT_BEACON_MAX_LIMIT (65535)
514 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
515 #define MLX4_EN_MAC_HASH_IDX 5
516
517 struct mlx4_en_stats_bitmap {
518 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
519 struct mutex mutex; /* for mutual access to stats bitmap */
520 };
521
522 enum {
523 MLX4_EN_STATE_FLAG_RESTARTING,
524 };
525
526 struct mlx4_en_priv {
527 struct mlx4_en_dev *mdev;
528 struct mlx4_en_port_profile *prof;
529 struct net_device *dev;
530 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
531 struct mlx4_en_port_state port_state;
532 spinlock_t stats_lock;
533 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
534 /* To allow rules removal while port is going down */
535 struct list_head ethtool_list;
536
537 unsigned long last_moder_packets[MAX_RX_RINGS];
538 unsigned long last_moder_tx_packets;
539 unsigned long last_moder_bytes[MAX_RX_RINGS];
540 unsigned long last_moder_jiffies;
541 int last_moder_time[MAX_RX_RINGS];
542 u16 rx_usecs;
543 u16 rx_frames;
544 u16 tx_usecs;
545 u16 tx_frames;
546 u32 pkt_rate_low;
547 u16 rx_usecs_low;
548 u32 pkt_rate_high;
549 u16 rx_usecs_high;
550 u32 sample_interval;
551 u32 adaptive_rx_coal;
552 u32 msg_enable;
553 u32 loopback_ok;
554 u32 validate_loopback;
555
556 struct mlx4_hwq_resources res;
557 int link_state;
558 bool port_up;
559 int port;
560 int registered;
561 int allocated;
562 int stride;
563 unsigned char current_mac[ETH_ALEN + 2];
564 int mac_index;
565 unsigned max_mtu;
566 int base_qpn;
567 int cqe_factor;
568 int cqe_size;
569
570 struct mlx4_en_rss_map rss_map;
571 __be32 ctrl_flags;
572 u32 flags;
573 u8 num_tx_rings_p_up;
574 u32 tx_work_limit;
575 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
576 u32 rx_ring_num;
577 u32 rx_skb_size;
578 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
579 u8 num_frags;
580 u8 log_rx_info;
581 u8 dma_dir;
582 u16 rx_headroom;
583
584 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
585 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
586 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
587 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
588 struct mlx4_qp drop_qp;
589 struct work_struct rx_mode_task;
590 struct work_struct restart_task;
591 struct work_struct linkstate_task;
592 struct delayed_work stats_task;
593 struct delayed_work service_task;
594 struct mlx4_en_pkt_stats pkstats;
595 struct mlx4_en_counter_stats pf_stats;
596 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
597 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
598 struct mlx4_en_flow_stats_rx rx_flowstats;
599 struct mlx4_en_flow_stats_tx tx_flowstats;
600 struct mlx4_en_port_stats port_stats;
601 struct mlx4_en_xdp_stats xdp_stats;
602 struct mlx4_en_phy_stats phy_stats;
603 struct mlx4_en_stats_bitmap stats_bitmap;
604 struct list_head mc_list;
605 struct list_head curr_list;
606 u64 broadcast_id;
607 struct mlx4_en_stat_out_mbox hw_stats;
608 int vids[128];
609 bool wol;
610 struct device *ddev;
611 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
612 struct hwtstamp_config hwtstamp_config;
613 u32 counter_index;
614
615 #ifdef CONFIG_MLX4_EN_DCB
616 #define MLX4_EN_DCB_ENABLED 0x3
617 struct ieee_ets ets;
618 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
619 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
620 struct mlx4_en_cee_config cee_config;
621 u8 dcbx_cap;
622 #endif
623 #ifdef CONFIG_RFS_ACCEL
624 spinlock_t filters_lock;
625 int last_filter_id;
626 struct list_head filters;
627 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
628 #endif
629 u64 tunnel_reg_id;
630 __be16 vxlan_port;
631
632 u32 pflags;
633 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
634 u8 rss_hash_fn;
635 unsigned long state;
636 };
637
638 enum mlx4_en_wol {
639 MLX4_EN_WOL_MAGIC = (1ULL << 61),
640 MLX4_EN_WOL_ENABLED = (1ULL << 62),
641 };
642
643 struct mlx4_mac_entry {
644 struct hlist_node hlist;
645 unsigned char mac[ETH_ALEN + 2];
646 u64 reg_id;
647 struct rcu_head rcu;
648 };
649
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)650 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
651 {
652 return buf + idx * cqe_sz;
653 }
654
655 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
656
657 void mlx4_en_init_ptys2ethtool_map(void);
658 void mlx4_en_update_loopback_state(struct net_device *dev,
659 netdev_features_t features);
660
661 void mlx4_en_destroy_netdev(struct net_device *dev);
662 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
663 struct mlx4_en_port_profile *prof);
664
665 int mlx4_en_start_port(struct net_device *dev);
666 void mlx4_en_stop_port(struct net_device *dev, int detach);
667
668 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
669 struct mlx4_en_stats_bitmap *stats_bitmap,
670 u8 rx_ppp, u8 rx_pause,
671 u8 tx_ppp, u8 tx_pause);
672
673 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
674 struct mlx4_en_priv *tmp,
675 struct mlx4_en_port_profile *prof,
676 bool carry_xdp_prog);
677 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
678 struct mlx4_en_priv *tmp);
679
680 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
681 int entries, int ring, enum cq_type mode, int node);
682 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
683 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
684 int cq_idx);
685 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
686 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
687 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
688
689 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
690 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
691 struct net_device *sb_dev);
692 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
693 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
694 struct mlx4_en_rx_alloc *frame,
695 struct mlx4_en_priv *priv, unsigned int length,
696 int tx_ind, bool *doorbell_pending);
697 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
698 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
699 struct mlx4_en_rx_alloc *frame);
700
701 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
702 struct mlx4_en_tx_ring **pring,
703 u32 size, u16 stride,
704 int node, int queue_index);
705 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
706 struct mlx4_en_tx_ring **pring);
707 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
708 struct mlx4_en_tx_ring *ring);
709 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
710 struct mlx4_en_tx_ring *ring,
711 int cq, int user_prio);
712 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
713 struct mlx4_en_tx_ring *ring);
714 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
715 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
716 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
717 struct mlx4_en_rx_ring **pring,
718 u32 size, u16 stride, int node, int queue_index);
719 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
720 struct mlx4_en_rx_ring **pring,
721 u32 size, u16 stride);
722 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
723 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
724 struct mlx4_en_rx_ring *ring);
725 int mlx4_en_process_rx_cq(struct net_device *dev,
726 struct mlx4_en_cq *cq,
727 int budget);
728 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
729 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
730 int mlx4_en_process_tx_cq(struct net_device *dev,
731 struct mlx4_en_cq *cq, int napi_budget);
732 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
733 struct mlx4_en_tx_ring *ring,
734 int index, u64 timestamp,
735 int napi_mode);
736 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
737 struct mlx4_en_tx_ring *ring,
738 int index, u64 timestamp,
739 int napi_mode);
740 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
741 int is_tx, int rss, int qpn, int cqn, int user_prio,
742 struct mlx4_qp_context *context);
743 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
744 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
745 int loopback);
746 void mlx4_en_calc_rx_buf(struct net_device *dev);
747 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
748 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
749 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
750 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
751 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
752 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
753
754 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
755 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
756
757 void mlx4_en_fold_software_stats(struct net_device *dev);
758 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
759 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
760
761 #ifdef CONFIG_MLX4_EN_DCB
762 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
763 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
764 #endif
765
766 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
767 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
768
769 #ifdef CONFIG_RFS_ACCEL
770 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
771 #endif
772
773 #define MLX4_EN_NUM_SELF_TEST 5
774 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
775 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
776
777 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
778 ((dev->features & feature) ^ (new_features & feature))
779
780 int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
781 int mlx4_en_reset_config(struct net_device *dev,
782 struct hwtstamp_config ts_config,
783 netdev_features_t new_features);
784 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
785 struct mlx4_en_stats_bitmap *stats_bitmap,
786 u8 rx_ppp, u8 rx_pause,
787 u8 tx_ppp, u8 tx_pause);
788 int mlx4_en_netdev_event(struct notifier_block *this,
789 unsigned long event, void *ptr);
790
791 /*
792 * Functions for time stamping
793 */
794 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
795 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
796 struct skb_shared_hwtstamps *hwts,
797 u64 timestamp);
798 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
799 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
800
801 /* Globals
802 */
803 extern const struct ethtool_ops mlx4_en_ethtool_ops;
804
805
806
807 /*
808 * printk / logging functions
809 */
810
811 __printf(3, 4)
812 void en_print(const char *level, const struct mlx4_en_priv *priv,
813 const char *format, ...);
814
815 #define en_dbg(mlevel, priv, format, ...) \
816 do { \
817 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
818 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
819 } while (0)
820 #define en_warn(priv, format, ...) \
821 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
822 #define en_err(priv, format, ...) \
823 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
824 #define en_info(priv, format, ...) \
825 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
826
827 #define mlx4_err(mdev, format, ...) \
828 pr_err(DRV_NAME " %s: " format, \
829 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
830 #define mlx4_info(mdev, format, ...) \
831 pr_info(DRV_NAME " %s: " format, \
832 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
833 #define mlx4_warn(mdev, format, ...) \
834 pr_warn(DRV_NAME " %s: " format, \
835 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
836
837 #endif
838