Searched refs:merge_3d (Results 1 – 11 of 11) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_merge3d.c | 25 if (idx == m->merge_3d[i].id) { in _merge_3d_offset()
26 b->blk_addr = addr + m->merge_3d[i].base; in _merge_3d_offset()
28 return &m->merge_3d[i]; in _merge_3d_offset()
35 static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, in dpu_hw_merge_3d_setup_3d_mode() argument
42 c = &merge_3d->hw; in dpu_hw_merge_3d_setup_3d_mode()
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| D | dpu_rm.c | 136 const struct dpu_merge_3d_cfg *merge_3d = &cat->merge_3d[i]; in dpu_rm_init() local
138 if (merge_3d->id < MERGE_3D_0 || merge_3d->id >= MERGE_3D_MAX) { in dpu_rm_init()
139 DPU_ERROR("skip merge_3d %d with invalid id\n", merge_3d->id); in dpu_rm_init()
142 hw = dpu_hw_merge_3d_init(merge_3d->id, mmio, cat); in dpu_rm_init()
149 rm->merge_3d_blks[merge_3d->id - MERGE_3D_0] = &hw->base; in dpu_rm_init()
167 if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX) in dpu_rm_init()
168 hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]); in dpu_rm_init()
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| D | dpu_encoder_phys_wb.c | 212 if (mode_3d && hw_pp && hw_pp->merge_3d) in dpu_encoder_phys_wb_setup_cdp()
213 intf_cfg.merge_3d = hw_pp->merge_3d->idx; in dpu_encoder_phys_wb_setup_cdp()
215 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode) in dpu_encoder_phys_wb_setup_cdp()
216 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_phys_wb_setup_cdp()
317 if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d) in _dpu_encoder_phys_wb_update_flush()
319 hw_pp->merge_3d->idx); in _dpu_encoder_phys_wb_update_flush()
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| D | dpu_encoder_phys_vid.c | 276 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
277 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
291 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
292 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
429 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_enable()
430 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_phys_vid_enable()
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| D | dpu_hw_ctl.c | 283 enum dpu_merge_3d merge_3d) in dpu_hw_ctl_update_pending_flush_merge_3d_v1() argument
285 ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0); in dpu_hw_ctl_update_pending_flush_merge_3d_v1()
549 if (cfg->merge_3d) in dpu_hw_ctl_intf_cfg_v1()
551 BIT(cfg->merge_3d - MERGE_3D_0)); in dpu_hw_ctl_intf_cfg_v1()
607 if (cfg->merge_3d) { in dpu_hw_ctl_reset_intf_cfg_v1()
609 merge3d_active &= ~BIT(cfg->merge_3d - MERGE_3D_0); in dpu_hw_ctl_reset_intf_cfg_v1()
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| D | dpu_hw_merge3d.h | 21 void (*setup_3d_mode)(struct dpu_hw_merge_3d *merge_3d,
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| D | dpu_hw_pingpong.h | 151 struct dpu_hw_merge_3d *merge_3d; member
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| D | dpu_hw_ctl.h | 49 enum dpu_merge_3d merge_3d; member
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| D | dpu_hw_catalog.h | 602 u32 merge_3d; member
847 const struct dpu_merge_3d_cfg *merge_3d; member
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| D | dpu_encoder.c | 2053 if (phys_enc->hw_pp->merge_3d) { in dpu_encoder_helper_phys_cleanup()
2054 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_helper_phys_cleanup()
2058 phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_helper_phys_cleanup()
2069 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_helper_phys_cleanup()
2070 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_helper_phys_cleanup()
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| D | dpu_hw_catalog.c | 1121 .merge_3d = _merge_3d, \
1131 .merge_3d = _merge_3d, \
1816 .merge_3d = sm8150_merge_3d,
1840 .merge_3d = sm8150_merge_3d,
1866 .merge_3d = sm8150_merge_3d,
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