Home
last modified time | relevance | path

Searched refs:mec_int_cntl (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c5761 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v11_0_set_compute_eop_interrupt_state() local
5794 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
5795 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5797 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5799 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5802 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
5803 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5805 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5807 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
Dgfx_v7_0.c4718 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4751 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4752 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4753 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4756 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4757 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4758 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c5533 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
5566 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5567 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5569 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5572 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5573 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5575 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6446 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6479 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6480 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6481 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6484 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6485 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6486 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c8993 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
9026 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9027 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9029 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9032 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9033 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
9035 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()