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Searched refs:mclk_table (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c752 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
820 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
822 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
824 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
826 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
827 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
915 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
917 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
918 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
920 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
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Dvega10_processpptables.c602 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
607 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), in get_mclk_voltage_dependency_table()
609 if (!mclk_table) in get_mclk_voltage_dependency_table()
612 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
615 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
617 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
619 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
621 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
625 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dsmu10_hwmgr.c966 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
996 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
1001 mclk_table->entries[low].clk/100, in smu10_force_clock_level()
1006 mclk_table->entries[high].clk/100, in smu10_force_clock_level()
1021 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
1052 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
1055 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
1056 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
Dvega10_hwmgr.c668 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
695 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
696 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
697 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
699 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
700 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
702 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
703 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3398 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3415 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
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Dprocess_pptables_v1_0.c367 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
374 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), in get_mclk_voltage_dependency_table()
376 if (!mclk_table) in get_mclk_voltage_dependency_table()
379 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
384 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
395 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dsmu7_hwmgr.h105 struct smu7_single_dpm_table mclk_table; member
Dvega12_hwmgr.c2691 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2694 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
Dvega20_hwmgr.c1516 struct vega20_single_dpm_table *mclk_table = in vega20_get_mclk_od() local
1520 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in vega20_get_mclk_od()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dci_dpm.c2517 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2520 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3297 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3298 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3301 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3309 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3319 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3321 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3323 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3428 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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Dci_dpm.h70 struct ci_single_dpm_table mclk_table; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1382 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1383 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1385 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1667 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1761 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
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Dvegam_smumgr.c1050 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1051 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1055 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1068 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1070 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1072 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1076 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1289 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1292 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
1381 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in vegam_populate_smc_boot_level()
Dfiji_smumgr.c1234 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1239 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1257 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1259 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1261 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1533 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1536 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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Dci_smumgr.c1317 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1318 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1320 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1330 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1340 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1341 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
1342 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in ci_populate_all_memory_levels()
1662 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1665 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1707 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
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Dpolaris10_smumgr.c1223 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1228 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1230 if (i == dpm_table->mclk_table.count - 1) in polaris10_populate_all_memory_levels()
1237 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1239 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1499 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1505 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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Dtonga_smumgr.c1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1130 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1131 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1133 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1545 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
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