Searched refs:max_tile_pipes (Results 1 – 19 of 19) sorted by relevance
379 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()381 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()383 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()385 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()387 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()389 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1206 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1226 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1250 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1270 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1332 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1347 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3161 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3183 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3205 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3228 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3250 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3272 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3300 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3322 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3344 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3366 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2046 unsigned max_tile_pipes; member2068 unsigned max_tile_pipes; member2095 unsigned max_tile_pipes; member2122 unsigned max_tile_pipes; member2160 unsigned max_tile_pipes; member2191 unsigned max_tile_pipes; member
2008 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2024 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2042 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2057 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2088 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3100 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3117 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3135 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3152 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3169 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3206 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
895 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()919 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2346 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3179 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3196 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3213 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3232 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3267 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
138 unsigned max_tile_pipes; member
1587 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()1604 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()1621 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1638 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1655 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
4252 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4269 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()4286 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4305 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()4330 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
726 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
1690 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1707 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1754 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1771 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1788 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1805 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1830 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
718 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
4252 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
2039 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
4506 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
1668 uint8_t max_tile_pipes; member1688 uint8_t max_tile_pipes; member1789 uint8_t max_tile_pipes; member
5653 UCHAR max_tile_pipes; member5666 UCHAR max_tile_pipes; member