Searched refs:max_backends_per_se (Results 1 – 20 of 20) sorted by relevance
696 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()714 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()735 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()1590 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1607 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1624 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1641 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()1658 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
141 unsigned max_backends_per_se; member
1631 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()1791 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()1809 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()4255 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4272 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()4288 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4308 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
1693 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1710 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()1757 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1773 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1790 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()1808 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()3461 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()3623 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()3641 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
729 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
1313 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()1347 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
792 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
721 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
1531 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v11_0_get_rb_active_bitmap()1542 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v11_0_setup_rb()
2310 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()2321 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
2010 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
4830 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()4842 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
897 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()935 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()949 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()963 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()970 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()1091 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1095 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1125 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()1137 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
359 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()362 *value = rdev->config.si.max_backends_per_se * in radeon_info_ioctl()365 *value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()
3103 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3120 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3138 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3155 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()3172 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()3289 rdev->config.si.max_backends_per_se); in si_gpu_init()
2124 unsigned max_backends_per_se; member2163 unsigned max_backends_per_se; member2194 unsigned max_backends_per_se; member
2330 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()3182 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3199 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()3215 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3235 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()3337 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
1671 uint8_t max_backends_per_se; member1691 uint8_t max_backends_per_se; member1716 uint8_t max_backends_per_se; member1751 uint8_t max_backends_per_se; member1792 uint8_t max_backends_per_se; member
5656 UCHAR max_backends_per_se; member5669 UCHAR max_backends_per_se; member