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Searched refs:lower_32_bits (Results 1 – 25 of 631) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/amdkfd/
Dkfd_packet_manager_v9.c55 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
62 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
66 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
70 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
100 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_aldebaran()
101 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_aldebaran()
105 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
109 lower_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
148 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
173 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
[all …]
Dkfd_packet_manager_vi.c69 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
108 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
133 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
136 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
186 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
192 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
264 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
266 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
Dkfd_mqd_manager_v11.c139 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
155 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
197 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
200 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
202 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
223 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
339 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
343 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_vi.c117 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
131 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
133 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
143 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
185 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
188 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
190 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
216 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
378 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
380 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v10.c113 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
129 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
171 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
174 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
176 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
197 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
338 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
340 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
/linux-6.1.9/drivers/firmware/smccc/
Dkvm_guest.c33 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
34 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
35 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
36 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
/linux-6.1.9/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.c151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c346 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
358 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
366 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
374 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
412 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
433 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
453 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
465 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
909 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
920 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
[all …]
Dsdma_v6_0.c109 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v6_0_ring_init_cond_exec()
220 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
233 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
238 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
283 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v6_0_ring_emit_ib()
288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
367 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
369 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
378 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
[all …]
Dsdma_v5_2.c150 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
236 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
249 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
253 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
298 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
303 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
306 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
382 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
384 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
393 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
[all …]
Dvcn_v2_5.c414 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
425 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
433 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
441 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
478 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
499 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
519 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
531 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
896 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
907 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
[all …]
Dvcn_v3_0.c460 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
471 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
479 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
487 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
523 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
544 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
564 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
576 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1066 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1077 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
[all …]
Dsi_dma.c71 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
157 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
223 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
276 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
323 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
324 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
347 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
350 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
390 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in si_dma_vm_set_pte_pde()
430 amdgpu_ring_write(ring, lower_32_bits(addr)); in si_dma_ring_emit_pipeline_sync()
[all …]
Dsdma_v5_0.c285 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
401 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
414 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
419 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
466 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
471 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
474 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
552 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
554 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
563 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
[all …]
Dsdma_v2_4.c260 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v2_4_ring_emit_ib()
265 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
318 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
320 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
326 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
454 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
566 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
621 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
675 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v2_4_vm_copy_pte()
677 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v2_4_vm_copy_pte()
[all …]
Dvcn_v1_0.c317 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
337 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
387 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
399 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
409 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
925 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
936 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
942 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
943 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
[all …]
Dsdma_v3_0.c434 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
492 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
494 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
500 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
693 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
715 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
838 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
893 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib()
946 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v3_0_vm_copy_pte()
[all …]
/linux-6.1.9/drivers/iio/test/
Diio-test-format.c211 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
217 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
223 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
229 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
235 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
241 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
247 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgm20b.c83 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
86 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
89 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
105 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
109 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
111 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux-6.1.9/arch/x86/include/asm/
Dmshyperv.h58 u32 input_address_lo = lower_32_bits(input_address); in hv_do_hypercall()
60 u32 output_address_lo = lower_32_bits(output_address); in hv_do_hypercall()
93 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall8()
126 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall16()
128 u32 input2_lo = lower_32_bits(input2); in hv_do_fast_hypercall16()
/linux-6.1.9/drivers/pci/controller/
Dpci-xgene.c291 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
295 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
388 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
390 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
392 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
400 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
449 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
452 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
515 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
521 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/linux-6.1.9/drivers/media/pci/pt3/
Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux-6.1.9/drivers/misc/habanalabs/common/
Dmemory_mgr.c25 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_get()
68 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_release()
87 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_remove_idr_locked()
119 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_put_handle()
186 idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_alloc()
/linux-6.1.9/include/linux/
Dgoldfish.h23 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_ptr()
33 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_dma_addr()

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