| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gfx.c | 299 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init_ring() local
302 spin_lock_init(&kiq->ring_lock); in amdgpu_gfx_kiq_init_ring()
307 ring->doorbell_index = adev->doorbell_index.kiq; in amdgpu_gfx_kiq_init_ring()
313 ring->eop_gpu_addr = kiq->eop_gpu_addr; in amdgpu_gfx_kiq_init_ring()
331 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_fini() local
333 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); in amdgpu_gfx_kiq_fini()
341 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init() local
344 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, in amdgpu_gfx_kiq_init()
345 &kiq->eop_gpu_addr, (void **)&hpd); in amdgpu_gfx_kiq_init()
353 r = amdgpu_bo_reserve(kiq->eop_obj, true); in amdgpu_gfx_kiq_init()
[all …]
|
| D | mes_v10_1.c | 883 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in mes_v10_1_kiq_enable_queue() local
884 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in mes_v10_1_kiq_enable_queue()
887 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v10_1_kiq_enable_queue()
890 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v10_1_kiq_enable_queue()
896 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
949 spin_lock_init(&adev->gfx.kiq.ring_lock); in mes_v10_1_kiq_ring_init()
951 ring = &adev->gfx.kiq.ring; in mes_v10_1_kiq_ring_init()
977 ring = &adev->gfx.kiq.ring; in mes_v10_1_mqd_sw_init()
1066 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, in mes_v10_1_sw_fini()
1067 &adev->gfx.kiq.ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
[all …]
|
| D | mes_v11_0.c | 929 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in mes_v11_0_kiq_enable_queue() local
930 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in mes_v11_0_kiq_enable_queue()
933 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v11_0_kiq_enable_queue()
936 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v11_0_kiq_enable_queue()
942 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v11_0_kiq_enable_queue()
959 ring = &adev->gfx.kiq.ring; in mes_v11_0_queue_init()
1026 spin_lock_init(&adev->gfx.kiq.ring_lock); in mes_v11_0_kiq_ring_init()
1028 ring = &adev->gfx.kiq.ring; in mes_v11_0_kiq_ring_init()
1054 ring = &adev->gfx.kiq.ring; in mes_v11_0_mqd_sw_init()
1145 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, in mes_v11_0_sw_fini()
[all …]
|
| D | gmc_v11_0.c | 280 if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && in gmc_v11_0_flush_gpu_tlb()
316 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v11_0_flush_gpu_tlb_pasid()
317 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v11_0_flush_gpu_tlb_pasid() local
320 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v11_0_flush_gpu_tlb_pasid()
322 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v11_0_flush_gpu_tlb_pasid()
323 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v11_0_flush_gpu_tlb_pasid()
328 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v11_0_flush_gpu_tlb_pasid()
333 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v11_0_flush_gpu_tlb_pasid()
|
| D | gmc_v10_0.c | 334 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && in gmc_v10_0_flush_gpu_tlb()
423 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v10_0_flush_gpu_tlb_pasid()
424 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v10_0_flush_gpu_tlb_pasid() local
427 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
429 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v10_0_flush_gpu_tlb_pasid()
430 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v10_0_flush_gpu_tlb_pasid()
435 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
440 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
|
| D | gmc_v9_0.c | 790 if (adev->gfx.kiq.ring.sched.ready && in gmc_v9_0_flush_gpu_tlb()
900 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v9_0_flush_gpu_tlb_pasid()
901 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v9_0_flush_gpu_tlb_pasid() local
916 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; in gmc_v9_0_flush_gpu_tlb_pasid()
919 ndw += kiq->pmf->invalidate_tlbs_size; in gmc_v9_0_flush_gpu_tlb_pasid()
921 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
925 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
927 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
932 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
938 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
|
| D | gfx_v11_0.c | 194 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx11_kiq_unmap_queues()
262 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
1284 struct amdgpu_kiq *kiq; in gfx_v11_0_sw_init() local
1408 kiq = &adev->gfx.kiq; in gfx_v11_0_sw_init()
1409 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v11_0_sw_init()
1477 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v11_0_sw_fini()
3308 adev->gfx.kiq.ring.sched.ready = enable; in gfx_v11_0_cp_compute_enable()
3516 (adev->doorbell_index.kiq * 2) << 2); in gfx_v11_0_cp_set_doorbell_range()
3699 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v11_0_kiq_enable_kgq() local
3700 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v11_0_kiq_enable_kgq()
[all …]
|
| D | amdgpu_virt.c | 73 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait() local
74 struct amdgpu_ring *ring = &kiq->ring; in amdgpu_virt_kiq_reg_write_reg_wait()
85 spin_lock_irqsave(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
94 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
116 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
|
| D | amdgpu_amdkfd_gfx_v10.c | 291 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
306 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
333 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
|
| D | amdgpu_amdkfd_gfx_v11.c | 263 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v11()
278 spin_lock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v11()
305 spin_unlock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v11()
|
| D | amdgpu_amdkfd_gfx_v9.c | 303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
318 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
345 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
|
| D | amdgpu_doorbell.h | 42 uint32_t kiq; member
|
| D | vega10_reg_init.c | 60 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; in vega10_doorbell_index_init()
|
| D | gfx_v10_0.c | 3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx10_kiq_unmap_queues()
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4586 struct amdgpu_kiq *kiq; in gfx_v10_0_sw_init() local
4630 &adev->gfx.kiq.irq); in gfx_v10_0_sw_init()
4717 kiq = &adev->gfx.kiq; in gfx_v10_0_sw_init()
4718 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v10_0_sw_init()
4775 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v10_0_sw_fini()
6296 adev->gfx.kiq.ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
6606 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_enable_kgq() local
6607 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_enable_kgq()
[all …]
|
| D | amdgpu_amdkfd_gfx_v10_3.c | 278 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
293 spin_lock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
320 spin_unlock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
|
| D | vega20_reg_init.c | 60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
|
| D | gfx_v9_0.c | 888 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
2106 struct amdgpu_kiq *kiq; in gfx_v9_0_sw_init() local
2223 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
2224 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v9_0_sw_init()
2254 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v9_0_sw_fini()
3193 adev->gfx.kiq.ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3475 (adev->doorbell_index.kiq * 2) << 2); in gfx_v9_0_kiq_init_register()
3646 ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_resume()
3825 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, in gfx_v9_0_hw_fini()
3826 adev->gfx.kiq.ring.pipe, in gfx_v9_0_hw_fini()
[all …]
|
| D | amdgpu_gfx.h | 280 struct amdgpu_kiq kiq; member
|
| D | gfx_v8_0.c | 1931 struct amdgpu_kiq *kiq; in gfx_v8_0_sw_init() local
2051 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2052 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v8_0_sw_init()
2081 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v8_0_sw_fini()
4322 adev->gfx.kiq.ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4344 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4694 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2); in gfx_v8_0_set_mec_doorbell_range()
4706 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4769 ring = &adev->gfx.kiq.ring; in gfx_v8_0_cp_test_all_rings()
4836 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kcq_disable()
[all …]
|
| D | soc21.c | 464 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc21_init_doorbell_index()
|
| D | nv.c | 598 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
|
| D | vi.c | 2239 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()
|