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Searched refs:intel_de_write (Results 1 – 25 of 50) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_vdsc.c611 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
618 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
621 intel_de_write(dev_priv, in intel_dsc_pps_configure()
625 intel_de_write(dev_priv, in intel_dsc_pps_configure()
635 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
642 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
645 intel_de_write(dev_priv, in intel_dsc_pps_configure()
649 intel_de_write(dev_priv, in intel_dsc_pps_configure()
660 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
667 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
[all …]
Dintel_fdi.c303 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); in cpt_set_fdi_bc_bifurcation()
349 intel_de_write(dev_priv, reg, temp); in intel_fdi_normal_train()
360 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); in intel_fdi_normal_train()
368 intel_de_write(dev_priv, reg, in intel_fdi_normal_train()
386 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), in ilk_fdi_link_train()
398 intel_de_write(dev_priv, reg, temp); in ilk_fdi_link_train()
409 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); in ilk_fdi_link_train()
415 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); in ilk_fdi_link_train()
421 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
423 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
[all …]
Dvlv_dsi.c111 intel_de_write(dev_priv, reg, val); in write_data()
173 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
183 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
239 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
246 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
342 intel_de_write(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
349 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
358 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
393 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in glk_dsi_device_ready()
402 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
[all …]
Dintel_pch_display.c124 intel_de_write(dev_priv, hdmi_reg, val); in ibx_sanitize_pch_hdmi_port()
143 intel_de_write(dev_priv, dp_reg, val); in ibx_sanitize_pch_dp_port()
220 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
222 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), in ilk_pch_transcoder_set_timings()
224 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
227 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
229 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), in ilk_pch_transcoder_set_timings()
231 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
233 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), in ilk_pch_transcoder_set_timings()
263 intel_de_write(dev_priv, reg, val); in ilk_enable_pch_transcoder()
[all …]
Dicl_dsi.c163 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); in dsi_send_pkt_payld()
200 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
228 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); in icl_dsi_frame_update()
249 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
264 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
272 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
280 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
291 intel_de_write(dev_priv, in dsi_program_swing_and_deemphasis()
328 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); in configure_dual_link_mode()
[all …]
Dintel_combo_phy.c95 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in icl_set_procmon_ref_values()
97 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
98 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
321 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
358 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
366 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
371 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
379 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); in icl_combo_phys_init()
384 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_init()
388 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); in icl_combo_phys_init()
[all …]
Dintel_tv.c931 intel_de_write(dev_priv, TV_CTL, in intel_enable_tv()
944 intel_de_write(dev_priv, TV_CTL, in intel_disable_tv()
1396 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); in set_tv_mode_timings()
1397 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); in set_tv_mode_timings()
1398 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); in set_tv_mode_timings()
1399 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); in set_tv_mode_timings()
1400 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); in set_tv_mode_timings()
1401 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); in set_tv_mode_timings()
1402 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); in set_tv_mode_timings()
1403 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_backlight.c209 intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
219 intel_de_write(dev_priv, BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
247 intel_de_write(dev_priv, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
258 intel_de_write(dev_priv, VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
267 intel_de_write(dev_priv, in bxt_set_backlight()
350 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, in lpt_disable_backlight()
355 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
367 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
370 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
386 intel_de_write(dev_priv, BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
Dg4x_hdmi.c57 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); in intel_hdmi_prepare()
163 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in g4x_enable_hdmi()
191 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
193 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
205 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, in ibx_enable_hdmi()
213 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
215 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
253 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
260 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
267 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
[all …]
Dintel_vrr.c192 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); in intel_vrr_enable()
193 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); in intel_vrr_enable()
194 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl); in intel_vrr_enable()
195 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); in intel_vrr_enable()
196 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); in intel_vrr_enable()
208 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), in intel_vrr_send_push()
233 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); in intel_vrr_disable()
234 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); in intel_vrr_disable()
Dintel_audio.c325 intel_de_write(dev_priv, reg_elda, tmp); in intel_eld_uptodate()
350 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
379 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
383 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, in g4x_audio_codec_enable()
388 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
423 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
436 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
469 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
478 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
509 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_audio_codec_disable()
[all …]
Dintel_fifo_underrun.c103 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
122 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
156 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
169 intel_de_write(dev_priv, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
209 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), in bdw_set_fifo_underrun_reporting()
243 intel_de_write(dev_priv, SERR_INT, in cpt_check_pch_fifo_underruns()
259 intel_de_write(dev_priv, SERR_INT, in cpt_set_fifo_underrun_reporting()
420 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns); in intel_cpu_fifo_underrun_irq_handler()
Dvlv_dsi_pll.c311 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_disable()
377 intel_de_write(dev_priv, MIPI_CTRL(port), in vlv_dsi_reset_clocks()
421 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
423 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
478 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
550 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
564 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_enable()
590 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
594 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); in bxt_dsi_reset_clocks()
598 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); in bxt_dsi_reset_clocks()
[all …]
Dintel_display_power_well.c359 intel_de_write(dev_priv, regs->driver, in hsw_power_well_enable()
388 intel_de_write(dev_priv, regs->driver, in hsw_power_well_disable()
405 intel_de_write(dev_priv, regs->driver, in icl_combo_phy_aux_power_well_enable()
410 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_enable()
421 intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val); in icl_combo_phy_aux_power_well_enable()
437 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_disable()
441 intel_de_write(dev_priv, regs->driver, in icl_combo_phy_aux_power_well_disable()
512 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); in icl_tc_phy_aux_power_well_enable()
515 intel_de_write(dev_priv, regs->driver, in icl_tc_phy_aux_power_well_enable()
651 intel_de_write(dev_priv, DC_STATE_EN, state); in gen9_write_dc_state()
[all …]
Dintel_dpio_phy.c294 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
300 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
311 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
316 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
320 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
393 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
415 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
420 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
426 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
431 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
[all …]
Dintel_hdcp.c293 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
294 intel_de_write(dev_priv, HDCP_KEY_STATUS, in intel_hdcp_clear_keys()
332 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
345 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
353 intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
420 intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
437 intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
456 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
489 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
498 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
[all …]
Dintel_hdmi.c215 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
218 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
223 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
229 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
247 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_read_infoframe()
289 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
292 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
298 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
304 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
323 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); in ibx_read_infoframe()
[all …]
Dintel_fbc.c278 intel_de_write(i915, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
296 intel_de_write(i915, FBC_TAG(i), 0); in i8xx_fbc_activate()
299 intel_de_write(i915, FBC_CONTROL2, in i8xx_fbc_activate()
301 intel_de_write(i915, FBC_FENCE_OFF, in i8xx_fbc_activate()
305 intel_de_write(i915, FBC_CONTROL, in i8xx_fbc_activate()
341 intel_de_write(i915, FBC_CFB_BASE, in i8xx_fbc_program_cfb()
343 intel_de_write(i915, FBC_LL_BASE, in i8xx_fbc_program_cfb()
419 intel_de_write(i915, DPFC_FENCE_YOFF, in g4x_fbc_activate()
422 intel_de_write(i915, DPFC_CONTROL, in g4x_fbc_activate()
435 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
[all …]
Dintel_pps.c108 intel_de_write(dev_priv, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
111 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
114 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
612 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
678 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
797 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
805 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
813 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
858 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
902 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_backlight_on()
[all …]
Dintel_dpll_mgr.c492 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_enable()
493 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_enable()
495 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
506 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
516 intel_de_write(dev_priv, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
603 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
611 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
623 intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
641 intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
1269 intel_de_write(dev_priv, DPLL_CTRL1, val); in skl_ddi_pll_write_ctrl1()
[all …]
Dintel_pch_refclk.c18 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); in lpt_fdi_reset_mphy()
26 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); in lpt_fdi_reset_mphy()
114 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); in lpt_disable_iclkip()
231 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); in lpt_program_iclkip()
617 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
636 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
647 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
661 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
Dg4x_dp.c147 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); in intel_dp_prepare()
212 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_on()
227 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_on()
246 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_off()
426 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
430 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
450 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
454 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
579 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in cpt_set_link_train()
607 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in g4x_set_link_train()
[all …]
Dintel_dvo.c198 intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
216 intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
313 intel_de_write(dev_priv, dvo_srcdim_reg, in intel_dvo_pre_enable()
315 intel_de_write(dev_priv, dvo_reg, dvo_val); in intel_dvo_pre_enable()
467 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
475 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_lvds.c215 intel_de_write(dev_priv, PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
217 intel_de_write(dev_priv, PP_ON_DELAYS(0), in intel_lvds_pps_init_hw()
220 intel_de_write(dev_priv, PP_OFF_DELAYS(0), in intel_lvds_pps_init_hw()
223 intel_de_write(dev_priv, PP_DIVISOR(0), in intel_lvds_pps_init_hw()
303 intel_de_write(dev_priv, lvds_encoder->reg, temp); in intel_pre_enable_lvds()
318 intel_de_write(dev_priv, lvds_encoder->reg, in intel_enable_lvds()
321 intel_de_write(dev_priv, PP_CONTROL(0), in intel_enable_lvds()
340 intel_de_write(dev_priv, PP_CONTROL(0), in intel_disable_lvds()
346 intel_de_write(dev_priv, lvds_encoder->reg, in intel_disable_lvds()
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_suspend.c68 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); in intel_restore_swf()
69 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
72 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); in intel_restore_swf()
75 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
78 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); in intel_restore_swf()
79 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
82 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); in intel_restore_swf()
119 intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()

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