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Searched refs:intel_de_read (Results 1 – 25 of 56) sorted by relevance

123

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_fdi.c33 cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
35 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
57 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
86 cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; in assert_fdi_tx_pll_enabled()
95 cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; in assert_fdi_rx_pll()
211 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; in intel_fdi_pll_freq_update()
286 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
291 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
294 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
341 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
[all …]
Dintel_pch_display.c101 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
111 u32 val = intel_de_read(dev_priv, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
130 u32 val = intel_de_read(dev_priv, dp_reg); in ibx_sanitize_pch_dp_port()
221 intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
223 intel_de_read(dev_priv, HBLANK(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
225 intel_de_read(dev_priv, HSYNC(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
228 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
230 intel_de_read(dev_priv, VBLANK(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
232 intel_de_read(dev_priv, VSYNC(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
234 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
[all …]
Dintel_combo_phy.c59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
92 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
105 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
167 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
169 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
171 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
318 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
349 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
362 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
368 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
[all …]
Dicl_dsi.c53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
60 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
132 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
181 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
226 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); in icl_dsi_frame_update()
244 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); in dsi_program_swing_and_deemphasis()
251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); in dsi_program_swing_and_deemphasis()
266 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
274 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
[all …]
Dvlv_dsi.c122 u32 val = intel_de_read(dev_priv, reg); in read_data()
242 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
341 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
347 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
353 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
354 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
371 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
392 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
398 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
399 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_display_power_well.c283 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
284 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
286 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
287 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
309 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & in hsw_wait_for_power_well_disable()
358 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enable()
387 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_disable()
404 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_enable()
409 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); in icl_combo_phy_aux_power_well_enable()
419 val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)); in icl_combo_phy_aux_power_well_enable()
[all …]
Dintel_backlight.c145 return intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
152 return intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
161 val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
182 return intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in vlv_get_backlight()
190 return intel_de_read(dev_priv, in bxt_get_backlight()
208 u32 val = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
218 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
246 tmp = intel_de_read(dev_priv, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
257 tmp = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
346 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_dpll_mgr.c461 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
463 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
464 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
478 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
622 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
640 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
665 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
685 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1155 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1262 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
[all …]
Dintel_pps.c60 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
74 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
84 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
241 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
247 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
264 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
417 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
430 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
444 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
445 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); in intel_pps_check_power_unlocked()
[all …]
Dintel_audio.c317 tmp = intel_de_read(dev_priv, reg_eldv); in intel_eld_uptodate()
323 tmp = intel_de_read(dev_priv, reg_elda); in intel_eld_uptodate()
328 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
341 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_disable()
348 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
364 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_enable()
376 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
386 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
411 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); in hsw_dp_audio_config_update()
425 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); in hsw_dp_audio_config_update()
[all …]
Dintel_dpio_phy.c292 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_levels()
296 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
302 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
313 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
318 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_levels()
330 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
333 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
341 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
353 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
391 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_lvds.c91 val = intel_de_read(dev_priv, lvds_reg); in intel_lvds_port_enabled()
131 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
149 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
162 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
164 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
169 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
173 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
210 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
319 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
322 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
Dintel_pch_refclk.c16 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
20 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
24 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
28 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
239 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
402 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in spll_uses_pch_ssc()
403 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
422 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in wrpll_uses_pch_ssc()
423 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
536 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); in ilk_init_pch_refclk()
[all …]
Dintel_dvo.c141 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
156 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
172 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
195 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
199 intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
210 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
217 intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
301 dvo_val = intel_de_read(dev_priv, dvo_reg) & in intel_dvo_pre_enable()
466 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
Dvlv_dsi_pll.c270 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
284 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
309 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
361 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
375 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
442 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
562 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
585 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
592 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
596 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
Dintel_fifo_underrun.c99 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
126 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
149 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
180 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
236 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
269 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
418 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & in intel_cpu_fifo_underrun_irq_handler()
Dintel_display_power.c1032 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; in gen9_dbuf_slice_set()
1131 u32 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_assert_cdclk()
1158 I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1160 I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1162 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1164 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1166 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
1168 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1171 I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1173 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
[all …]
Dintel_vrr.c221 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
244 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); in intel_vrr_get_config()
257 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; in intel_vrr_get_config()
258 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; in intel_vrr_get_config()
259 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; in intel_vrr_get_config()
Dg4x_dp.c118 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
142 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); in intel_dp_prepare()
172 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; in assert_dp_port()
183 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
257 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
281 val = intel_de_read(dev_priv, dp_reg); in g4x_dp_port_enabled()
348 tmp = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_get_config()
353 u32 trans_dp = intel_de_read(dev_priv, in intel_dp_get_config()
388 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) in intel_dp_get_config()
412 (intel_de_read(dev_priv, intel_dp->output_reg) & in intel_dp_link_down()
[all …]
Dintel_tv.c912 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
932 intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
945 intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1100 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1101 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1102 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1103 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1104 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1139 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1143 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
[all …]
Dintel_ddi.c176 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
193 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_active()
309 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()
593 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_disable_transcoder_func()
638 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_toggle_hdcp_bits()
676 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_connector_get_hw_state()
734 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
739 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
780 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
819 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); in intel_ddi_get_encoder_pipes()
[all …]
Dintel_crt.c83 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
120 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
468 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
492 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
527 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
543 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
594 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
741 u32 vsync = intel_de_read(dev_priv, vsync_reg); in intel_crt_load_detect()
958 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
1009 adpa = intel_de_read(dev_priv, adpa_reg); in intel_crt_init()
[all …]
Dintel_display.c297 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); in skl_wa_827()
300 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); in skl_wa_827()
310 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
313 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
394 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; in pipe_scanline_is_moving()
396 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; in pipe_scanline_is_moving()
455 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in assert_transcoder()
525 intel_de_read(dev_priv, dpll_reg) & port_mask, in vlv_wait_port_ready()
569 val = intel_de_read(dev_priv, reg); in intel_enable_transcoder()
608 val = intel_de_read(dev_priv, reg); in intel_disable_transcoder()
[all …]
Dintel_hdmi.c73 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
82 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
204 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
242 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_read_infoframe()
250 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); in g4x_read_infoframe()
257 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
278 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
318 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
326 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
335 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
[all …]
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()

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