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Searched refs:intel_de_posting_read (Results 1 – 25 of 30) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_fdi.c304 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
363 intel_de_posting_read(dev_priv, reg); in intel_fdi_normal_train()
417 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
453 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
507 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
536 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
546 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
591 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
601 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
653 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
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Dg4x_hdmi.c58 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
164 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in g4x_enable_hdmi()
192 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
194 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
207 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
214 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
216 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
261 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
268 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
303 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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Dg4x_dp.c213 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
228 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
247 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_off()
427 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
431 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
451 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
455 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
580 intel_de_posting_read(dev_priv, intel_dp->output_reg); in cpt_set_link_train()
608 intel_de_posting_read(dev_priv, intel_dp->output_reg); in g4x_set_link_train()
632 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_enable_port()
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Dintel_fifo_underrun.c104 intel_de_posting_read(dev_priv, reg); in i9xx_check_fifo_underruns()
124 intel_de_posting_read(dev_priv, reg); in i9xx_set_fifo_underrun_reporting()
157 intel_de_posting_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
245 intel_de_posting_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
Dintel_pps.c109 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
112 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
115 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
613 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
679 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
798 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
806 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
814 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
859 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_off_unlocked()
903 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_backlight_on()
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Dintel_pch_refclk.c618 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
637 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
648 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
662 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
Dintel_hdmi.c230 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
305 intel_de_posting_read(dev_priv, reg); in ibx_write_infoframe()
387 intel_de_posting_read(dev_priv, reg); in cpt_write_infoframe()
463 intel_de_posting_read(dev_priv, reg); in vlv_write_infoframe()
545 intel_de_posting_read(dev_priv, ctl_reg); in hsw_write_infoframe()
893 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
913 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
1065 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1086 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1122 intel_de_posting_read(dev_priv, reg); in cpt_set_infoframes()
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Dintel_pipe_crc.c620 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_set_crc_source()
655 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_enable_pipe_crc()
670 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_disable_pipe_crc()
Dintel_de.h20 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read() function
Dintel_dsb.c90 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_enable_engine()
108 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_disable_engine()
Dintel_dkl_phy.c106 intel_de_posting_read(i915, reg); in intel_dkl_phy_posting_read()
Dintel_vga.c45 intel_de_posting_read(dev_priv, vga_reg); in intel_vga_disable()
Dintel_dpll.c1572 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1590 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1721 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1751 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in vlv_enable_pll()
1923 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in chv_enable_pll()
1978 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1995 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
2021 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
Dintel_backlight.c524 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
560 intel_de_posting_read(dev_priv, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
574 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
604 intel_de_posting_read(dev_priv, BLC_PWM_CTL); in i9xx_enable_backlight()
647 intel_de_posting_read(dev_priv, BLC_PWM_CTL2); in i965_enable_backlight()
679 intel_de_posting_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
732 intel_de_posting_read(dev_priv, in bxt_enable_backlight()
768 intel_de_posting_read(dev_priv, in cnp_enable_backlight()
Dintel_dpll_mgr.c498 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
507 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
517 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_disable()
604 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
612 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_enable()
624 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
642 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
1270 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1283 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1284 intel_de_posting_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_enable()
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Dhsw_ips.c76 intel_de_posting_read(i915, IPS_CTL); in hsw_ips_disable()
Dintel_display_power.c1029 intel_de_posting_read(dev_priv, reg); in gen9_dbuf_slice_set()
1205 intel_de_posting_read(dev_priv, D_COMP_BDW); in hsw_write_dcomp()
1239 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1257 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1284 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
Dintel_lvds.c323 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
348 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
Dintel_crt.c487 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
962 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
Dicl_dsi.c376 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
382 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
389 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
711 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
Dvlv_dsi_pll.c551 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
Dintel_ddi.c1399 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2180 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_disable_fec_state()
2874 intel_de_posting_read(dev_priv, reg); in intel_enable_ddi_hdmi()
3114 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3129 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3137 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
Dintel_sdvo.c225 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
232 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
249 intel_de_posting_read(dev_priv, GEN3_SDVOB); in intel_sdvo_write_sdvox()
252 intel_de_posting_read(dev_priv, GEN3_SDVOC); in intel_sdvo_write_sdvox()
Dintel_tv.c1630 intel_de_posting_read(dev_priv, TV_DAC); in intel_tv_detect_type()
1662 intel_de_posting_read(dev_priv, TV_CTL); in intel_tv_detect_type()
Dintel_cdclk.c1021 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1117 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1132 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()

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