| /linux-6.1.9/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,infracfg.yaml | 4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
28 - mediatek,mt6797-infracfg
29 - mediatek,mt7622-infracfg
30 - mediatek,mt7629-infracfg
31 - mediatek,mt7986-infracfg
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| D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /linux-6.1.9/drivers/soc/mediatek/ |
| D | mtk-infracfg.c | 28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
70 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
79 struct regmap *infracfg; in mtk_infracfg_init() local
87 infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); in mtk_infracfg_init()
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| D | mtk-pm-domains.c | 46 struct regmap *infracfg; member
149 ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_enable()
193 return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_disable()
355 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); in scpsys_add_one_domain()
356 if (IS_ERR(pd->infracfg)) in scpsys_add_one_domain()
357 return ERR_CAST(pd->infracfg); in scpsys_add_one_domain()
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| /linux-6.1.9/arch/arm64/boot/dts/mediatek/ |
| D | mt8183.dtsi | 659 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
667 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
675 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
683 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
691 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
699 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
707 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
715 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
726 infracfg: syscon@10001000 { label
727 compatible = "mediatek,mt8183-infracfg", "syscon";
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| D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
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| D | mt8192.dtsi | 280 infracfg: syscon@10001000 { label
281 compatible = "mediatek,mt8192-infracfg", "syscon";
333 <&infracfg CLK_INFRA_AUDIO_26M_B>,
334 <&infracfg CLK_INFRA_AUDIO>;
336 mediatek,infracfg = <&infracfg>;
342 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
344 mediatek,infracfg = <&infracfg>;
358 mediatek,infracfg = <&infracfg>;
399 mediatek,infracfg = <&infracfg>;
413 mediatek,infracfg = <&infracfg>;
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| D | mt7986a.dtsi | 109 infracfg: infracfg@10001000 { label
110 compatible = "mediatek,mt7986-infracfg", "syscon";
181 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
191 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
192 <&infracfg CLK_INFRA_UART0_CK>;
195 <&infracfg CLK_INFRA_UART0_SEL>;
206 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
207 <&infracfg CLK_INFRA_UART1_CK>;
209 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
219 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
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| D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
212 infracfg: infracfg@10000000 { label
213 compatible = "mediatek,mt7622-infracfg",
224 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
226 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
249 infracfg = <&infracfg>;
258 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
303 clocks = <&infracfg CLK_INFRA_TRNG>;
623 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
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| D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: power-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
482 mediatek,infracfg = <&infracfg>;
516 mediatek,infracfg = <&infracfg>;
534 clocks = <&infracfg CLK_INFRA_CLK_13M>,
543 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
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| D | mt8516.dtsi | 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
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| /linux-6.1.9/Documentation/devicetree/bindings/sound/ |
| D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg:
32 description: The phandle of the mediatek infracfg controller
63 - mediatek,infracfg
85 mediatek,infracfg = <&infracfg>;
91 <&infracfg CLK_INFRA_AUDIO>,
92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| D | mt8186-afe-pcm.yaml | 32 mediatek,infracfg:
34 description: The phandle of the mediatek infracfg controller
102 - mediatek,infracfg
121 mediatek,infracfg = <&infracfg>;
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| D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
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| /linux-6.1.9/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie-gen3.yaml | 163 clocks = <&infracfg 44>,
164 <&infracfg 40>,
165 <&infracfg 43>,
166 <&infracfg 97>,
167 <&infracfg 99>,
168 <&infracfg 111>;
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| /linux-6.1.9/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
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| /linux-6.1.9/Documentation/devicetree/bindings/soc/mediatek/ |
| D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
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| /linux-6.1.9/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
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| /linux-6.1.9/Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.yaml | 105 mediatek,infracfg:
107 description: The phandle to the mediatek infracfg syscon
188 - mediatek,infracfg
212 clocks = <&infracfg CLK_INFRA_M4U>;
214 mediatek,infracfg = <&infracfg>;
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| /linux-6.1.9/Documentation/devicetree/bindings/power/ |
| D | mediatek,power-controller.yaml | 112 mediatek,infracfg:
172 mediatek,infracfg = <&infracfg>;
206 mediatek,infracfg = <&infracfg>;
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
474 mediatek,infracfg = <&infracfg>;
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| D | mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
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| D | mt8135.dtsi | 133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
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| /linux-6.1.9/Documentation/devicetree/bindings/spmi/ |
| D | mtk,spmi-mtk-pmif.yaml | 67 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
68 <&infracfg CLK_INFRA_PMIC_TMR>,
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| /linux-6.1.9/Documentation/devicetree/bindings/phy/ |
| D | mediatek,ufs-phy.yaml | 63 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
64 <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
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