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Searched refs:imx_clk_hw_gate_dis (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/drivers/clk/imx/
Dclk-imx8ulp.c179 …clks[IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE] = imx_clk_hw_gate_dis("spll3_pfd0_div1_gate", "spll3_pfd0",… in imx8ulp_clk_cgc1_init()
180 …clks[IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE] = imx_clk_hw_gate_dis("spll3_pfd0_div2_gate", "spll3_pfd0",… in imx8ulp_clk_cgc1_init()
181 …clks[IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE] = imx_clk_hw_gate_dis("spll3_pfd1_div1_gate", "spll3_pfd1",… in imx8ulp_clk_cgc1_init()
182 …clks[IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE] = imx_clk_hw_gate_dis("spll3_pfd1_div2_gate", "spll3_pfd1",… in imx8ulp_clk_cgc1_init()
183 …clks[IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE] = imx_clk_hw_gate_dis("spll3_pfd2_div1_gate", "spll3_pfd2",… in imx8ulp_clk_cgc1_init()
184 …clks[IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE] = imx_clk_hw_gate_dis("spll3_pfd2_div2_gate", "spll3_pfd2",… in imx8ulp_clk_cgc1_init()
185 …clks[IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE] = imx_clk_hw_gate_dis("spll3_pfd3_div1_gate", "spll3_pfd3",… in imx8ulp_clk_cgc1_init()
186 …clks[IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE] = imx_clk_hw_gate_dis("spll3_pfd3_div2_gate", "spll3_pfd3",… in imx8ulp_clk_cgc1_init()
206 clks[IMX8ULP_CLK_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("sosc_div1_gate", "sosc", base + 0x108, 7); in imx8ulp_clk_cgc1_init()
207 clks[IMX8ULP_CLK_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("sosc_div2_gate", "sosc", base + 0x108, 15); in imx8ulp_clk_cgc1_init()
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Dclk-imx7d.c456 …hws[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m… in imx7d_clocks_init()
457 …hws[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m… in imx7d_clocks_init()
464 …hws[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m… in imx7d_clocks_init()
465 …hws[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m… in imx7d_clocks_init()
466 …hws[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m… in imx7d_clocks_init()
Dclk.h130 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
165 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ macro