| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | dcn301_smu.c | 218 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn301_smu_set_display_idle_optimization() argument
222 DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info); in dcn301_smu_set_display_idle_optimization()
227 idle_info); in dcn301_smu_set_display_idle_optimization()
232 union display_idle_optimization_u idle_info = { 0 }; in dcn301_smu_enable_phy_refclk_pwrdwn() local
235 idle_info.idle_info.df_request_disabled = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
236 idle_info.idle_info.phy_ref_clk_off = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
244 idle_info.data); in dcn301_smu_enable_phy_refclk_pwrdwn()
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| D | vg_clk_mgr.c | 121 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
123 idle_info.idle_info.df_request_disabled = 1; in vg_update_clocks()
124 idle_info.idle_info.phy_ref_clk_off = 1; in vg_update_clocks()
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
134 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
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| D | dcn301_smu.h | 145 struct display_idle_optimization idle_info; member
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_smu.c | 234 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn316_smu_set_display_idle_optimization() argument
246 idle_info); in dcn316_smu_set_display_idle_optimization()
251 union display_idle_optimization_u idle_info = { 0 }; in dcn316_smu_enable_phy_refclk_pwrdwn() local
257 idle_info.idle_info.df_request_disabled = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
258 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
264 idle_info.data); in dcn316_smu_enable_phy_refclk_pwrdwn()
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| D | dcn316_clk_mgr.c | 174 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
175 idle_info.idle_info.df_request_disabled = 1; in dcn316_update_clocks()
176 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_update_clocks()
177 idle_info.idle_info.s0i2_rdy = 1; in dcn316_update_clocks()
178 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
191 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
192 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
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| D | dcn316_smu.h | 118 struct display_idle_optimization idle_info; member
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_smu.c | 248 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn315_smu_set_display_idle_optimization() argument
260 idle_info); in dcn315_smu_set_display_idle_optimization()
265 union display_idle_optimization_u idle_info = { 0 }; in dcn315_smu_enable_phy_refclk_pwrdwn() local
271 idle_info.idle_info.df_request_disabled = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
272 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
278 idle_info.data); in dcn315_smu_enable_phy_refclk_pwrdwn()
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| D | dcn315_clk_mgr.c | 139 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
140 idle_info.idle_info.df_request_disabled = 1; in dcn315_update_clocks()
141 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_update_clocks()
142 idle_info.idle_info.s0i2_rdy = 1; in dcn315_update_clocks()
143 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
151 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
152 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
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| D | dcn315_smu.h | 110 struct display_idle_optimization idle_info; member
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_smu.c | 245 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn31_smu_set_display_idle_optimization() argument
257 idle_info); in dcn31_smu_set_display_idle_optimization()
262 union display_idle_optimization_u idle_info = { 0 }; in dcn31_smu_enable_phy_refclk_pwrdwn() local
268 idle_info.idle_info.df_request_disabled = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
269 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
275 idle_info.data); in dcn31_smu_enable_phy_refclk_pwrdwn()
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| D | dcn31_clk_mgr.c | 164 union display_idle_optimization_u idle_info = { 0 }; in dcn31_update_clocks() local
165 idle_info.idle_info.df_request_disabled = 1; in dcn31_update_clocks()
166 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_update_clocks()
167 idle_info.idle_info.s0i2_rdy = 1; in dcn31_update_clocks()
168 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
188 union display_idle_optimization_u idle_info = { 0 }; in dcn31_update_clocks() local
189 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
638 union display_idle_optimization_u idle_info = { 0 }; in dcn31_set_low_power_state() local
640 idle_info.idle_info.df_request_disabled = 1; in dcn31_set_low_power_state()
641 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_set_low_power_state()
[all …]
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| D | dcn31_smu.h | 250 struct display_idle_optimization idle_info; member
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_smu.c | 262 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn314_smu_set_display_idle_optimization() argument
274 idle_info); in dcn314_smu_set_display_idle_optimization()
279 union display_idle_optimization_u idle_info = { 0 }; in dcn314_smu_enable_phy_refclk_pwrdwn() local
285 idle_info.idle_info.df_request_disabled = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
286 idle_info.idle_info.phy_ref_clk_off = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
292 idle_info.data); in dcn314_smu_enable_phy_refclk_pwrdwn()
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| D | dcn314_smu.h | 89 struct display_idle_optimization idle_info; member
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| D | dcn314_clk_mgr.c | 195 union display_idle_optimization_u idle_info = { 0 }; in dcn314_update_clocks() local
196 idle_info.idle_info.df_request_disabled = 1; in dcn314_update_clocks()
197 idle_info.idle_info.phy_ref_clk_off = 1; in dcn314_update_clocks()
198 idle_info.idle_info.s0i2_rdy = 1; in dcn314_update_clocks()
199 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn314_update_clocks()
219 union display_idle_optimization_u idle_info = { 0 }; in dcn314_update_clocks() local
221 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn314_update_clocks()
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