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123

/linux-6.1.9/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument
278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument
298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument
300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument
330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC() argument
332 …ine uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT() argument
334 …uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT_REG() argument
371 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
385 …atic inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER() argument
387 … inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_REG() argument
[all …]
/linux-6.1.9/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument
348 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE() argument
360 …tic inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE() argument
362 … inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_OP() argument
382 …e uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_O… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
384 …e uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_O… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
[all …]
/linux-6.1.9/drivers/gpu/drm/msm/dsi/
Ddsi_phy_10nm.xml.h126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN() argument
128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG0() argument
130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG1() argument
132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG2() argument
134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3() argument
136 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_10nm_PHY_LN_TEST_DATAPATH() argument
138 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_PIN_SWAP() argument
140 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL() argument
142 …c inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL() argument
144 …c inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL() argument
[all …]
Ddsi_phy_14nm.xml.h117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN() argument
119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG0() argument
127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG1() argument
130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG2() argument
132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3() argument
134 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TEST_DATAPATH() argument
136 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_TEST_STR() argument
138 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4() argument
146 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5() argument
154 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6() argument
[all …]
Ddsi_phy_20nm.xml.h56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN() argument
58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_0() argument
60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_1() argument
62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_2() argument
64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3() argument
66 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_4() argument
68 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_20nm_PHY_LN_TEST_DATAPATH() argument
70 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_DEBUG_SEL() argument
72 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_0() argument
74 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_1() argument
Ddsi_phy_28nm.xml.h56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN() argument
58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0() argument
60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1() argument
62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2() argument
64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3() argument
66 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4() argument
68 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument
70 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument
72 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0() argument
74 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1() argument
Ddsi_phy_7nm.xml.h160 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN() argument
162 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG0() argument
164 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG1() argument
166 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG2() argument
168 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;… in REG_DSI_7nm_PHY_LN_TEST_DATAPATH() argument
170 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_PIN_SWAP() argument
172 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_LPRX_CTRL() argument
174 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_TX_DCTRL() argument
Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument
64 …nline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument
66 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument
68 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument
Dmmss_cc.xml.h71 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK() argument
73 …tic inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_CC() argument
90 …tic inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_MD() argument
104 …tic inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_NS() argument
/linux-6.1.9/drivers/gpu/drm/etnaviv/
Dstate.xml.h73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) argument
198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) argument
204 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) argument
206 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) argument
208 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) argument
210 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) argument
214 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) argument
[all …]
/linux-6.1.9/arch/sparc/lib/
Ddivdi3.S14 cmp %i0,0
21 sub %g0,%i0,%o0
23 mov %o4,%i0
42 cmp %o4,%i0
46 subcc %i0,%o4,%g0
49 sub %i0,%o4,%i0 ! this kills msb of n
50 addx %i0,%i0,%i0 ! so this cannot give carry
53 subcc %i0,%o4,%g0
57 sub %i0,%o4,%i0 ! this kills msb of n
58 4: sub %i0,%o4,%i0
[all …]
Dudivdi3.S17 cmp %o3,%i0
22 subcc %i0,%o3,%g0
25 sub %i0,%o3,%i0 ! this kills msb of n
26 addx %i0,%i0,%i0 ! so this cannot give carry
29 subcc %i0,%o3,%g0
33 sub %i0,%o3,%i0 ! this kills msb of n
34 4: sub %i0,%o3,%i0
35 5: addxcc %i0,%i0,%i0
41 sub %i0,%o3,%i0
49 mov %i0,%o2
[all …]
Dxor.S262 sub %i0, 64, %i0
305 subcc %i0, 64, %i0
364 srlx %i0, 6, %g1
365 mov %i1, %i0
372 ldda [%i0 + 0x00] %asi, %o0 /* %o0/%o1 = dest + 0x00 */
373 ldda [%i0 + 0x10] %asi, %o2 /* %o2/%o3 = dest + 0x10 */
374 ldda [%i0 + 0x20] %asi, %o4 /* %o4/%o5 = dest + 0x20 */
375 ldda [%i0 + 0x30] %asi, %l2 /* %l2/%l3 = dest + 0x30 */
376 prefetch [%i0 + 0x40], #n_writes
379 stxa %o0, [%i0 + 0x00] %asi
[all …]
DNGpage.S33 stxa %o2, [%i0 + 0x00] %asi
34 stxa %o3, [%i0 + 0x08] %asi
35 stxa %o4, [%i0 + 0x10] %asi
36 stxa %o5, [%i0 + 0x18] %asi
37 stxa %l2, [%i0 + 0x20] %asi
38 stxa %l3, [%i0 + 0x28] %asi
39 stxa %l4, [%i0 + 0x30] %asi
40 stxa %l5, [%i0 + 0x38] %asi
45 stxa %o2, [%i0 + 0x40] %asi
46 stxa %o3, [%i0 + 0x48] %asi
[all …]
Dmemcpy.S297 andcc %i0, 3, %g0
299 andcc %i0, 1, %g0
301 andcc %i0, 2, %g0
305 stb %g5, [%i0]
308 add %i0, 1, %i0
312 stb %g3, [%i0]
315 add %i0, 2, %i0
316 stb %g3, [%i0 - 1]
334 add %i0, -8, %i0
340 add %i0, -12, %i0
[all …]
DNGmemcpy.S87 add %i2, %i5, %i0
91 add %i2, %g1, %i0
96 add %i2, %g1, %i0
101 add %i2, %g1, %i0
106 add %i2, %g1, %i0
111 add %i2, %g1, %i0
116 add %i2, %g1, %i0
121 add %i2, %g1, %i0
126 add %i2, %g1, %i0
130 add %i2, %i4, %i0
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/linux-6.1.9/arch/arm64/crypto/
Daes-ce.S57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4
58 aes\de \i0\().16b, \k\().16b
59 aes\mc \i0\().16b, \i0\().16b
77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4
79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4
81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4
86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4
87 aes\de \i0\().16b, \k\().16b
98 eor \i0\().16b, \i0\().16b, \k2\().16b
112 .macro do_block_Nx, enc, rounds, i0, i1, i2, i3, i4
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/linux-6.1.9/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h971 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT() argument
973 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL() argument
991 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO() argument
1024 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE() argument
1026 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3() argument
1034 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL() argument
1537 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP() argument
1539 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN() argument
1541 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX() argument
1547 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP() argument
[all …]
Da6xx.xml.h1126 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH() argument
1128 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG() argument
1130 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT() argument
1132 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG() argument
1165 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } in REG_A6XX_CP_PERFCTR_CP_SEL() argument
1300 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } in REG_A6XX_RBBM_PERFCTR_CP() argument
1302 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } in REG_A6XX_RBBM_PERFCTR_RBBM() argument
1304 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } in REG_A6XX_RBBM_PERFCTR_PC() argument
1306 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } in REG_A6XX_RBBM_PERFCTR_VFD() argument
1308 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } in REG_A6XX_RBBM_PERFCTR_HLSQ() argument
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Da5xx.xml.h1034 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH() argument
1036 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH_REG() argument
1038 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT() argument
1040 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT_REG() argument
2133 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG() argument
2135 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG_REG() argument
2161 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } in REG_A5XX_VSC_PIPE_DATA_ADDRESS() argument
2163 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO() argument
2165 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI() argument
2167 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } in REG_A5XX_VSC_PIPE_DATA_LENGTH() argument
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Da3xx.xml.h915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT() argument
917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG() argument
1221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT() argument
1223 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL() argument
1246 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO() argument
1273 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_BASE() argument
1281 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } in REG_A3XX_RB_MRT_BLEND_CONTROL() argument
1880 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK() argument
1882 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0;… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE() argument
1884 …ic inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET() argument
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/linux-6.1.9/fs/jffs2/
Dcompr_rubin.c105 long i0, i1; in encode() local
119 i0 = A * rs->p / (A + B); in encode()
120 if (i0 <= 0) in encode()
121 i0 = 1; in encode()
123 if (i0 >= rs->p) in encode()
124 i0 = rs->p - 1; in encode()
126 i1 = rs->p - i0; in encode()
129 rs->p = i0; in encode()
132 rs->q += i0; in encode()
203 long i0, threshold; in decode() local
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/linux-6.1.9/tools/testing/selftests/proc/
Dproc-uptime-001.c28 uint64_t start, u0, u1, i0, i1; in main() local
34 proc_uptime(fd, &u0, &i0); in main()
39 assert(i1 >= i0); in main()
41 i0 = i1; in main()
Dproc-uptime-002.c48 uint64_t u0, u1, i0, i1; in main() local
63 proc_uptime(fd, &u0, &i0); in main()
73 assert(i1 >= i0); in main()
75 i0 = i1; in main()
/linux-6.1.9/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h178 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO() argument
182 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0() argument
186 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1() argument
188 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR() argument
190 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0() argument
198 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1() argument
395 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION() argument
397 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG() argument

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